tag: Onto Innovation

Why Wafer Bumps Are Suddenly So Important
By Anne Meixner - 10 Aug, 2021 - Comments: 2

Wafer bumps need to be uniform in height to facilitate subsequent manufacturing steps, but a push for 100% inspection in packaging in mission-critical markets is putting a strain on existing measurement technologies. Bump co-planarity is essentially a measure of flatness. Specifically, it measures the variation in bump height, which may have a target, for example, of about 100 microns. As a ... » read more

Who Owns In-Chip Monitoring Data?
By Bryon Moyer - 10 Aug, 2021 - Comments: 1

In-chip monitors provide unprecedented visibility into the inner workings of complex integrated circuits for everything from process control to fine binning, preventive system maintenance, and failure analysis. But there may be many consumers of different slices of the data at very different phases of the chip lifecycle, raising questions about who controls and owns all of that data. The ans... » read more

Extremely Large Exposure Field w/Fine Resolution Lithography Tech To Enable Next-Gen Panel Level Advanced Packaging
By Technical Paper Link - 05 Aug, 2021 - Comments: 0

Abstract—"The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Heterogeneous integration enables next-generation device per... » read more

The Great Quantum Computing Race
By Mark LaPedus - 26 Jul, 2021 - Comments: 0

Quantum computing is heating up, as a growing number of entities race to benchmark, stabilize, and ultimately commercialize this technology. As of July 2021, a group from China appears to have taken the lead in terms of raw performance, but Google, IBM, Intel and other quantum computer developers aren’t far behind. All of that could change overnight, though. At this point, it's too early t... » read more

Geo-Spatial Outlier Detection
By Anne Meixner - 19 Jul, 2021 - Comments: 0

Comparing die test results with other die on a wafer helps identify outliers, but combining that data with the exact location of an outlier offers a much deeper understanding of what can go wrong and why. The main idea in outlier detection is to find something in or on a die that is different from all the other dies on a wafer. Doing this in the context of a die’s neighbor has become easie... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 16 Jul, 2021 - Comments: 0

Chipmakers The chip industry is buzzing over a Wall Street Journal report that Intel is in talks to buy GlobalFoundries (GF) for $30 billion. In March, Intel re-entered the foundry business, positioning itself against Samsung and TSMC at the leading edge, and against a multitude of foundries working at older nodes. Intel planned to jumpstart its foundry business within its own fabs. But it... » read more

5G Chips Add Test Challenges
By Bryon Moyer - 06 Jul, 2021 - Comments: 1

The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Cleaning Up During IC Test
By Anne Meixner - 06 Jul, 2021 - Comments: 2

Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

What Does It Take To Build A Successful Multi-Chip Module Factory?
By Mike McIntyre - 06 Jul, 2021 - Comments: 0

When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t ex... » read more

IC Data Hot Potato: Who Owns And Manages It?
By Susan Rambo And Ed Sperling - 06 Jul, 2021 - Comments: 1

Modern inspection, metrology, and test equipment produces a flood of data during the manufacturing and testing of semiconductors. Now the question is what to do with all of that data. Image resolutions in inspection and metrology have been improving for some time to deal with increased density and smaller features, creating a downstream effect that has largely gone unmanaged. Higher resoluti... » read more

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