5G Chips Add Test Challenges


The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Cleaning Up During IC Test


Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

What Does It Take To Build A Successful Multi-Chip Module Factory?


When it comes to multi-chip module (MCM) manufacturing, fan-out wafer-level and fan-out panel-level packaging have received a lot of coverage recently. Every week, it seems like there is an announcement about “Company XYZ” moving their products into the fan-out wafer-level packaging (FOWLP) or fan-out panel-level packaging (FOPLP) space. But these moves come with challenges that didn’t ex... » read more

IC Data Hot Potato: Who Owns And Manages It?


Modern inspection, metrology, and test equipment produces a flood of data during the manufacturing and testing of semiconductors. Now the question is what to do with all of that data. Image resolutions in inspection and metrology have been improving for some time to deal with increased density and smaller features, creating a downstream effect that has largely gone unmanaged. Higher resoluti... » read more

There’s More To Machine Learning Than CNNs


Neural networks – and convolutional neural networks (CNNs) in particular – have received an abundance of attention over the last few years, but they're not the only useful machine-learning structures. There are numerous other ways for machines to learn how to solve problems, and there is room for alternative machine-learning structures. “Neural networks can do all this really comple... » read more

Reliability Costs Becoming Harder To Track


Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Expanded Material Metrology For Refined Etch Selectivities


Trends in advanced device fabrication require combined lithography-etching multi-patterning sequences and self-aligned multi-patterning to form devices’ finest features at subwavelength dimensions. As EUV lithography (13.5 nm) progresses to larger numerical apertures and new thin resists, new multipatterning sequences must be developed with mutually compatible resists and proximal layers t... » read more

Fab Fingerprint For Proactive Yield Management


The following paper presents a case study describing how to improve yield and fab productivity by implementing a frequent pattern database that utilizes artificial intelligence-based spatial pattern recognition (SPR) and wafer process history. This is important because associating spatial yield issues with process and tools is often performed as a reactive analysis, resulting in increased wafer... » read more

Demand, Lead Times Soar For 300mm Equipment


A surge in demand for various chips is causing select shortages and extended lead times for many types of 300mm semiconductor equipment, photomask tools, wafers, and other products. For the last several years, 200mm equipment has been in short supply in the market, but issues are now cropping up throughout the 300mm supply chain, as well. Traditionally, lead times have been three to six mont... » read more

Advanced Packaging’s Next Wave


Packaging houses are readying the next wave of advanced packages, enabling new system-level chip designs for a range of applications. These advanced packages involve a range of technologies, such as 2.5D/3D, chiplets, fan-out and system-in-package (SiP). Each of these, in turn, offers an array of options for assembling and integrating complex dies in an advanced package, providing chip custo... » read more

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