Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues


Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Improving Yield With Machine Learning


Machine learning is becoming increasingly valuable in semiconductor manufacturing, where it is being used to improve yield and throughput. This is especially important in process control, where data sets are noisy. Neural networks can identify patterns that exceed human capability, or perform classification faster. Consequently, they are being deployed across a variety of manufacturing proce... » read more

E-beam’s Role Grows For Detecting IC Defects


The perpetual march toward smaller features, coupled with growing demand for better reliability over longer chip lifetimes, has elevated inspection from a relatively obscure but necessary technology into one of the most critical tools in fab and packaging houses. For years, inspection had been framed as a battle between e-beam and optical microscopy. Increasingly, though, other types of insp... » read more

Deep Learning Delivers Fast, Accurate Solutions For Object Detection In The Automated Optical Inspection Of Electronic Assemblies


When automated optical inspection (AOI) works, it is almost always preferable to human visual inspection. It can be faster, more accurate, more consistent, less expensive, and it never gets tired. However, some tasks that are very simple for humans are quite difficult for machines. Object detection is an example. For example, shown an image containing a cat, a dog, and a duck, a human can insta... » read more

Gearing Up For High-NA EUV


The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task. ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems... » read more

Inspecting, Testing, And Measuring SiC


Achieving the auto industry's stringent zero defect goals is becoming a big challenge for makers of silicon carbide substrates, which are struggling to achieve sufficient yields and reliability as they migrate from 150mm to 200mm wafers and shift their focus away from pure silicon. SiC is a combination of silicon and harder carbide materials, and it has emerged as a key technology for batter... » read more

Addressing High Precision Automated Optical Inspection Challenges With Unique 3D Technology Solution


Driven by the continued decrease in the size of electronics packaging, combined with the increase in density, there is a critical need for highly accurate 3D inspection for defect detection. Using multi-view 3D sensors and parallel projection, it is possible to capture more of the board at a faster rate as compared to serial image acquisition, which is more time consuming. Precise 3D image r... » read more

Fabs Drive Deeper Into Machine Learning


Advanced machine learning is beginning to make inroads into yield enhancement methodology as fabs and equipment makers seek to identify defectivity patterns in wafer images with greater accuracy and speed. Each month a wafer fabrication factory produces tens of millions of wafer-level images from inspection, metrology, and test. Engineers must analyze that data to improve yield and to reject... » read more

Understanding Optical Inspection For CIS


The demand for smartphone cameras, video conferencing, surveillance and autonomous driving has fueled explosive growth of CMOS image sensor (CIS) manufacturing in the last decade. While CIS becomes an increasingly important element in the production of today’s consumer electronics, there are unique challenges in production that must be addressed. As pixel sizes shrink, we see an inverse relat... » read more

Hunting For Open Defects In Advanced Packages


Catching all defects in chip packaging is becoming more difficult, requiring a mix of electrical tests, metrology screening, and various types of inspection. And the more critical the application for these chips, the greater the effort and the cost. Latent open defects continue to be the bane of test, quality, and reliability engineering. Open defects in packages occur at the chip-to-substra... » read more

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