tag: packaging

Fix Processes, Then Silos
By Ed Sperling - 09 Feb, 2017 - Comments: 0

Jack Welch, former CEO of GE, was a big proponent of what he called a "boundaryless corporation." It was a good sound bite, but it pales in comparison to former Intel CEO Andy Grove's philosophy of working out of a cubicle, just like the rest of his staff. While it's great to have corporate buy-in for breaking down silos, which are vertically integrated, the real problem for semiconductor c... » read more

Electrothermal Mechanical Stress Reference Design Flow For Printed Circuit Boards And Electronic Packages
By Ansys - 08 Feb, 2017 - Comments: 0

This paper presents a reference design flow for solving the electrical, thermal and mechanical challenges of a printed circuit board (PCB) using simulation tools from ANSYS. This approach can be utilized for all electrical CAD (ECAD) types such as IC packages, touch panel displays, and glass and silicon interposers. The authors followed this reference design flow for analyzing a PCB virtual pro... » read more

OSAT Biz: Growth And Challenges
By Mark LaPedus - 08 Feb, 2017 - Comments: 0

Amid a challenging business environment, the outsourced semiconductor assembly and test (OSAT) industry is projected to see steady to strong growth in a number of packaging segments this year. Right now, the [getkc id="83" kc_name="OSATs"]—which provide third-party IC-packaging and test services—are seeing brisk demand for both legacy and advanced chip packages. In addition, IDMs continu... » read more

2017: Manufacturing And Markets
By Brian Bailey - 12 Jan, 2017 - Comments: 0

While the industry is busy chatting about the end of Moore's Law and a maturing of the semiconductor industry, the top minds of many companies are having none of it. A slowdown in one area is just an opportunity, in another and that is reflected in the predictions for this year. As in previous years, Semiconductor Engineering will look back on these predictions at the end of the year to see ... » read more

Stacked Die Changes
By Ed Sperling - 15 Sep, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Noise Killed My Chip
By Brian Bailey - 08 Sep, 2016 - Comments: 0

In the past, noise was considered an annoyance, especially for analog circuitry. But today chips are actually failing because insufficient analysis was performed. Noise types that used to be second-order effects are becoming primary factors that have to be considered. This is happening at the same time that noise margins are getting smaller, both in the amplitude and temporal dimensions. It ... » read more

Surprises At Hot Chips 2016
By Ed Sperling - 25 Aug, 2016 - Comments: 0

Who would have thought an Intel architect would be on stage talking about cutting pennies out of MCU prices? Or that Nvidia would be trumpeting an automotive SoC whose chief performance advantages come from the integration of ARM CPUs that can support up to eight virtual machines? Or that Samsung would be developing a quad-core mobile processor from scratch based on its own unique architecture?... » read more

Stacking Logic On Logic
By Katherine Derbyshire - 21 Jul, 2016 - Comments: 0

Advanced packaging can be an alphabet soup of possible approaches, from heterogenous integration of multiple die types into a single package, to three-dimensional stacking of multiple dies on top of each other. Three-dimensional chip stacking is most commonly seen in memory devices. Applied to logic, though, there are at least two different ways for integration to proceed. Completely process... » read more

Plotting The Next Semiconductor Road Map
By Ed Sperling - 13 Jun, 2016 - Comments: 0

The semiconductor industry is retrenching around new technologies and markets as Moore's Law becomes harder to sustain and growth rates in smart phones continue to flatten. In the past, it was a sure bet that pushing to the next process node would provide improvements in power, performance and cost. But after 22nm, the economics change due to the need for multi-patterning and finFETs, and th... » read more

Foundries Expand Their Scope
By Ed Sperling - 21 Apr, 2016 - Comments: 0

By Ed Sperling & Mark LaPedus Major foundries are stepping up their offerings across a wide swath of technology nodes, specialty processes and advanced packaging—a recognition that end markets are fragmenting and that the path forward includes a mix of new and established processes. As the smart phone market flattens, there is no single "next big thing" to drive volume at the most ... » read more

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