tag: packaging

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)
By John Chang - 08 Nov, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

Heterogeneous Integration: Exposing Large Panels With Fewer Shots
By John Chang - 11 Oct, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration is one tool helping accomplish these gains by combining multiple silicon nodes and designs inside one pac... » read more

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO
By Nathan Whitchurch - 15 Sep, 2022 - Comments: 0

Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

Heterogeneous IC Packaging: Optimizing Performance And Cost
By Mike Kelly - 18 Aug, 2022 - Comments: 0

Leading integrated circuit (IC) foundries are already shipping 7-nm and 5-nm wafers and 3-nm product qualifications are ongoing. Wafer costs continue to soar as high transistor density requires ever more expensive processes to fabricate them. Even if defect densities can remain relatively flat as new nodes emerge, the cost per unit area of silicon increases nonlinearly. These economics have pla... » read more

IC Package Illustrations, From 2D To 3D
By Tyler DeHaan - 21 Jul, 2022 - Comments: 1

In five words or less can you describe what a semiconductor is? Some might say a computer chip, others may say they are "space magic," but I would venture that most people have never heard the word before and would simply say "I have no idea." I was certainly a part of the latter crowd before I began my internship with Amkor Technology where I was brought on board as a 3D illustrator to create ... » read more

Packaging Solutions For Unique Markets
By Marc Mangrum - 16 Jun, 2022 - Comments: 0

The MicroLeadframe (MLF/QFN) packaging technology is the fastest growing IC packaging solution today. From a market segment perspective, MLF packaging solutions represent a >111B-unit market for 2022 across 5 unique markets: automotive, consumer, industrial, computing/networking, and communications. The package solution requirements across these markets varies but, the fundamental values the... » read more

The Race To Zero Defects In Auto ICs
By Anne Meixner - 07 Jun, 2022 - Comments: 0

Assembly houses are fine-tuning their methodologies and processes for automotive ICs, optimizing everything from inspection and metrology to data management in order to prevent escapes and reduce the number of costly returns. Today, assembly defects account for between 12% and 15% of semiconductor customer returns in the automotive chip market. As component counts in vehicles climb from the ... » read more

Challenges For Achieving Automotive Grade 1/0 Reliability In FCBGA and fcCSP Packages
By Knowlton Olmstead - 21 Apr, 2022 - Comments: 0

As the quantity, complexity, and functions of electronic devices in automobiles increase, understanding and characterizing package reliability is of significant concern and importance. The Automotive Electronics Council (AEC) Q-100 specification for Grade 1 and 0 reliability introduces unique challenges as thermal cycling (TC) and high temperature storage (HTS) requirements increase. Additional... » read more

Nip The Defect In The Bud
By Melvin Lee - 12 Apr, 2022 - Comments: 0

As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed, and assembl... » read more

Finding And Applying Domain Expertise In IC Analytics
By Anne Meixner - 12 Apr, 2022 - Comments: 0

Behind PowerPoint slides depicting the data inputs and outputs of a data analytics platform belies the complexity, effort, and expertise that improve fab yield. With the tsunami of data collected for semiconductor devices, fabs need engineers with domain expertise to effectively manage the data and to correctly learn from the data. Naively analyzing a data set can lead to an uninteresting an... » read more

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