UCIe: Marketing Ruins It Again

By Brian Bailey - 24 Mar, 2022 - Comments: 1

You may have seen the press release and articles recently about a new standard called UCIe. It stands for Universal Chiplet Interconnect Express. The standard is a great idea and will certainly help the market for chiplet-based designs to advance. But the name — Argggh. More on that later. First, let's talk about what it is. You may notice the name looks similar to PCIe (Peripheral Compone... » read more

Wirebond IC Substrates: Challenges Ahead

By Prasad Dhond - 17 Mar, 2022 - Comments: 0

Substrate suppliers are slashing capacity allocated to wirebond IC substrates. We hear about "limited tenting capacity," "no support for EBS designs," and requests for "conversion to etchback" designs. What does all this mean? Let's start with "Line" and "Space." "Line" is the width of a trace on a substrate and "Space" is the distance between the two traces. For wirebond packages such a... » read more

Addressing The ABF Substrate Shortage With In-Line Monitoring

By Wesley Chou - 08 Mar, 2022 - Comments: 1

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers. Looking ahead, the ABF substrate market will continue to grow, with revenue up ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II

By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Technology Advances, Shortages Seen For Wire Bonders

By Mark LaPedus - 17 Feb, 2022 - Comments: 2

A surge in demand for IC packages is causing long lead times for wire bonders, which are used to assemble three-fourths of the world’s packages. The wire bonder market doubled last year, alongside advanced packaging’s rise. Wirebonding is an older technology that typically flies under the radar. Still, packaging houses have multitudes of these key tools that help assemble many — but no... » read more

Thermal Management Implications For Heterogeneous Integrated Packaging

By Cameron Nelson - 17 Feb, 2022 - Comments: 1

As the semiconductor industry reaches lower process nodes, silicon designers struggle to have Moore's Law produce the results achieved in earlier generations. Increasing the die size in a monolithic system on chip (SoC) designs is no longer economically viable. The breakdown of monolithic SoCs into specialized chips, referred to as chiplets, presents significant benefits in terms of cost, yield... » read more

Thin Quad Die Package (QDP) Development

By Shaun Bowers - 20 Jan, 2022 - Comments: 0

In the world of solid-state memory fabs, bits per mm2 rule. In the memory packaging market, mm2 of silicon per a given package thickness is the defining feature. Both the memory architecture of the wafer and the package technology take advantage of 3D structures to achieve best in class bit density. In the case of the wafer fab, 3D NAND and other technologies are pushing the envelope to meet ev... » read more

Covid Masks And Forecasts At Semicon

By Mark LaPedus - 16 Dec, 2021 - Comments: 0

Semicon West 2021 was certainty different, if not surreal, this year. The annual event was held in-person from Dec. 7-9, although there is a virtual component that runs until Jan. 7, 2022. In comparison, Semicon West was an all-virtual event in 2020, due to the Covid-19 pandemic. At this year’s in-person event in San Francisco, attendees, exhibitors and speakers were all required to wea... » read more

Design Process And Methodology For Achieving High-Volume Production Quality For HDFO Packaging

By Ruben Fuentes - 16 Dec, 2021 - Comments: 0

Unlike the traditional system on chip (SoC) design process, which has fully qualified verification methods embodied in the form of process design kits (PDKs), chip design companies and outsourced semiconductor assembly and test (OSAT) suppliers have typically had no integrated circuit (IC) package co-design sign-off verification process to help ensure that an IC package will meet manufacturabil... » read more

Achieving Success In Automotive Leadframe Packages

By John Nickelsen - 22 Nov, 2021 - Comments: 0

The growth of semiconductor content in automotive applications has been accelerating. This growth drives all families of semiconductor packaging in all regions. The growth is happening in the latest advanced, laminate-based packages using flip chip interconnect as well as the venerable leadframe packages using wirebond interconnect. The automotive market consumes micro-electromechanical systems... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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