tag: PCIe

PCIe 6.0 Address Translation Services: Verification Challenges And Strategies
By Geeta Arora - 18 Jul, 2024 - Comments: 0

Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where devices need to access virtual memory. ATS enhances performance by enabling devices to cache translations, reducing the latency associated with memory access. This blog delves into the semantics ... » read more

Why PCIe 7.0 Over Optics
By Keivan Javadi Khasraghi - 13 Jun, 2024 - Comments: 0

By Keivan Javadi Khasraghi and Ruben Sousa Data centers are currently facing the increasing need to enhance their bandwidth capacities. This surge is largely driven by the rise of new technologies, especially the growing demand for AI and machine learning applications. As these technologies advance, bandwidth requirements are projected to expand dramatically. As Large Language Models (LLMs) ... » read more

PCIe 7.0 Takes Center Stage At PCI-SIG DevCon ’24
By Gautam S. - 13 Jun, 2024 - Comments: 0

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of i... » read more

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software
By Synopsys - 12 Jun, 2024 - Comments: 0

PCI Express (PCIe) 5.0 silicon characterization across process, voltage, and temperature variations, is necessary for accelerating SoC designs. To measure key qualifying parameters, designers and test engineers must have a good understanding of the PCIe 5.0 base electrical specification and know the physical layer’s design architecture and features for accurate characterization of 32GT/s PHY ... » read more

Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1
By Rambus - 05 Jun, 2024 - Comments: 0

The PCI Express (PCIe) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard. Find more inform... » read more

Rigorous Correlation Methodology for PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models
By Alphawave Semi - 24 Apr, 2024 - Comments: 0

IBIS-AMI models have been around for a decade and evolved to provide off-chip and system designers an efficient way to assess link performance of high-speed electrical interfaces with transceivers implementing various combination of equalization techniques [1]. As with any model, for IBIS-AMI to be useful they need to be benchmarked and carefully correlated to real-world silicon performance of ... » read more

PCI Express Test Overview
By Keysight - 10 Apr, 2024 - Comments: 0

PCl Express, short for Peripheral Component Interconnect Express, is a high-performance and high-bandwidth serial communication interconnect standard. First proposed by Intel and further developed by the Peripheral Component Interconnect Special Interest Group (PCI-SIG) in replacement of bus-based communication architecture, such as PCI, PCI Extended (PCI-X), and Accelerated Graphics Port (AGP)... » read more

NoCs In 3D Space
By Brian Bailey - 03 Apr, 2024 - Comments: 0

A network on chip (NoC) has become an essential piece of technology that enables the complexity of chips to keep growing, but when designs go 3D, or when third-party chiplets become pervasive, it's not clear how NoCs will evolve or what the impact will be on chiplet architectures. A NoC enables data to move between heterogeneous computing elements, while at the same time minimizing the resou... » read more

Building Scalable And Efficient Data Centers With CXL
By Lou Ternullo - 15 Feb, 2024 - Comments: 0

The AI boom is giving rise to profound changes in the data center; demanding AI workloads are driving an unprecedented need for low latency, high-bandwidth connectivity and flexible access to more memory and compute power when needed. The Compute Express Link (CXL) interconnect offers new ways for data centers to enhance performance and efficiency between CPUs, accelerators and storage and move... » read more

Unraveling PCIe 6.0 Loopback And Digital Near-End Loopback Feature
By Sabnam Sahoo - 21 Dec, 2023 - Comments: 0

The PCIe specification has given a specific Link Training and Status State Machine (LTSSM) state named Loopback, which is intended for test and fault isolation use. Basically, it gives a mechanism that involves looping back the data that was received in the Loopback LTSSM state. The entry and exit behavior are specified, and all other details are implementation-specific. Loopback can op... » read more

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