tag: PCIe

New Power, Performance Options At The Edge
By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

Retimers Replacing Redrivers As Signal Speeds Increase
By Bryon Moyer - 08 Jul, 2021 - Comments: 1

Retimers are undergoing a renaissance as new PHY protocols prove too demanding for redrivers. Redrivers and retimers both have been used to extend wired signal reach over the years. But redrivers have dominated this space due to their relative simplicity and lower cost. That balance is beginning to change. “A retimer represents three things no one wants in their system — area, cost, a... » read more

CXL Signals A New Era Of Data Center Architecture
By Tim Messegee - 08 Jul, 2021 - Comments: 0

An exponential rise in data volume and traffic across the global internet infrastructure is motivating exploration of new architectures for the data center. Disaggregation and composability would move us beyond the classic architecture of the server as the unit of computing. By separating the functional components of compute, memory, storage and networking into pools, composed on-demand to matc... » read more

Challenges In Developing A New Inferencing Chip
By Ed Sperling - 01 Jul, 2021 - Comments: 0

Cheng Wang, co-founder and senior vice president of software and engineering at Flex Logix, sat down with Semiconductor Engineering to explain the process of bringing an inferencing accelerator chip to market, from bring-up, programming and partitioning to tradeoffs involving speed and customization.   SE: Edge inferencing chips are just starting to come to market. What challenges di... » read more

Getting Ready For An Efficient Shift To PCI Express 6.0 Designs With Optimized IP
By Gary Ruggles - 10 Jun, 2021 - Comments: 0

PCI Express (PCIe) 6.0 technology with key changes will bring about challenges that high-performance computing, artificial intelligence, and storage system-on-chip (SoC) designers will face. This article provides designers a summary of the major changes and how they can be handled to ensure a smooth and successful transition to PCIe 6.0. The three major changes in PCIe 6.0 that designers nee... » read more

Next-Gen SerDes Roadmap
By Ed Sperling - 25 May, 2021 - Comments: 0

An explosion in data is causing a series of successive bottlenecks in the data center. Priyank Shukla, product marketing manager for high-speed SerDes IP at Synopsys, digs into the performance roadmap for moving data within server racks and between different racks, where the bottlenecks are today, and how they will be addressed in the future. Related SerDes Knowledge Center Top stories... » read more

PCI Express 5.0 Takes Center Stage For Data Centers
By Vinitha Seevaratnam - 08 Apr, 2021 - Comments: 0

The demands on servers at the heart of data centers continue an inexorable rise. Responding to these demands, new platforms keep coming that deliver greater computing performance, have more memory and use faster interconnects. On the way at the end of this year and early 2022 are new server platforms that will take performance to a new level. These new platforms will transition to DDR5 DIMMs fo... » read more

Safeguarding Data Over PCIe & CXL In Data Centers
By Dana Neustadter - 01 Apr, 2021 - Comments: 0

As more devices enter the market and drive exponential growth of data in the cloud, cloud computing is going through a significant overhaul. The increasing presence of “hyperscale” cloud providers for big data and analytics, 5G for rapid IoT connectivity, and the wide use of AI for natural data processing and for extracting insights are compounding both the amount of connected data and the ... » read more

Re-Architecting SerDes
By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Making IC Test Faster And More Accessible: Part 1
By Robert Ruiz - 30 Oct, 2020 - Comments: 0

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test vectors and then observe the chip to determine if it exhibits good or faulty behavior. There have been many innovations over the years to make the required testing of chips more tractable. Thanks ... » read more

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