tag: PDF Solutions

One Test Is Not Always Enough
By Anne Meixner - 12 Oct, 2021 - Comments: 0

To improve yield, quality, and cost, two separate test parameters can be combined to determine if a part passes or fails. The results gleaned from that approach are more accurate, allowing test and quality engineers to fail parts sooner, detect more test escapes, and ultimately to improve yield and reduce manufacturing costs. New data analytic platforms, combined with better utilization of s... » read more

Making Test Transparent With Better Data
By Susan Rambo - 07 Sep, 2021 - Comments: 0

Data is critical for a variety of processes inside the fab. The challenge is getting enough consistent data from different equipment and then plugging it back into the design, manufacturing, and test flows to quickly improve the process and uncover hard-to-find defective die. Progress is being made. The inspection and test industry is on the cusp of having more dynamic ways to access the dat... » read more

Designing Chips For Test Data
By Ed Sperling - 10 Aug, 2021 - Comments: 0

Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn't always so simple. It requires moving signals through a complex, sometimes unpredictable, and often hostile environment, which is a daunting challenge under the best of conditions. There is a growing sense of... » read more

Geo-Spatial Outlier Detection
By Anne Meixner - 19 Jul, 2021 - Comments: 0

Comparing die test results with other die on a wafer helps identify outliers, but combining that data with the exact location of an outlier offers a much deeper understanding of what can go wrong and why. The main idea in outlier detection is to find something in or on a die that is different from all the other dies on a wafer. Doing this in the context of a die’s neighbor has become easie... » read more

CEO Outlook: Chiplets, Longer IC Lifetimes, More End Markets
By Ed Sperling - 14 Jul, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss chiplets, longer IC lifetimes, and a spike in the number of end applications with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; an... » read more

Driving Toward Predictive Analytics With Dynamic Parametric Test
By Alan Hart - 06 Jul, 2021 - Comments: 0

The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabric... » read more

IC Data Hot Potato: Who Owns And Manages It?
By Susan Rambo And Ed Sperling - 06 Jul, 2021 - Comments: 1

Modern inspection, metrology, and test equipment produces a flood of data during the manufacturing and testing of semiconductors. Now the question is what to do with all of that data. Image resolutions in inspection and metrology have been improving for some time to deal with increased density and smaller features, creating a downstream effect that has largely gone unmanaged. Higher resoluti... » read more

CEO Outlook: More Data, More Integration, Same Deadlines
By Ed Sperling - 24 Jun, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss the future of chip design and EDA tools with Lip-Bu Tan, CEO of Cadence; Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of Siemens IC EDA; John Kibarian, CEO of PDF Solutions; Prakash Narain, president and CEO of Real Intent; Dean Drako, president and CEO of IC Manage; and Babak Taheri, CEO of Silvaco. What ... » read more

Reliability Costs Becoming Harder To Track
By Ed Sperling And Susan Rambo - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

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