tag: PDF Solutions

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Jul, 2018 - Comments: 0

Chipmakers TSMC has reduced its outlook for 2018 revenue and capital spending, according to Bloomberg. The company blamed the outlook on sluggish “mobile and digital currency mining demand,” according to the report. Samsung has developed the industry’s first 10nm-class 8-gigabit LPDDR5 DRAM. The 8Gb LPDDR5 boasts a data rate of up to 6,400 megabits-per-second (Mb/s), which is 1.5 tim... » read more

Estimating MOSFET Leakage From Low-Cost, Low-Resolution Fast Parametric Test
By PDF Solutions - 19 Jul, 2018 - Comments: 0

A method of estimating the subthershold component of MOSFET off-state current (Ioffs) using low-cost, low-resolution fast parallel parametric test is introduced. This method measures the subthreshold slope and uses it to estimate Ioffs. Measurements of individual transistors show a very good agreement between measured Ioffs and Ioffs estimated using our approach. For a simple pad-efficient tran... » read more

Dealing With Resistance In Chips
By Mark LaPedus - 21 Jun, 2018 - Comments: 2

Chipmakers continue to scale the transistor at advanced nodes, but they are struggling to maintain the same pace with the other two critical parts of the device—the contacts and interconnects. That’s beginning to change, however. In fact, at 10nm/7nm, chipmakers are introducing new topologies and materials such as cobalt, which promises to boost the performance and reduce unwanted resist... » read more

Big Trouble At 3nm
By Mark LaPedus - 21 Jun, 2018 - Comments: 0

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm. Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-p... » read more

FinFET Metrology Challenges Grow
By Mark LaPedus - 17 May, 2018 - Comments: 1

Chipmakers face a multitude of challenges in the fab at 10nm/7nm and beyond, but one technology that is typically under the radar is becoming especially difficult—metrology. Metrology, the art of measuring and characterizing structures, is used to pinpoint problems in devices and processes. It helps to ensure yields in both the lab and fab. At 28nm and above, metrology is a straightforward... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 11 May, 2018 - Comments: 0

Test and packaging In a major surprise, Cohu has entered into a definitive agreement to acquire Xcerra for approximately $796 million. With the deal, Cohu will enter the ATE market. Last year, a group from China entered into a definitive agreement under which it would acquire Xcerra. But the U.S. blocked Xcerra’s sale to the Chinese group. Ironically, at one time, Cohu was reportedly lobbyin... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

The Week In Review: Design
By Jesse Allen - 20 Jan, 2017 - Comments: 0

Legal Back in 2013, Synopsys filed suit against ATopTech for copyright infringement. The courts found in favor of Synopsys and ATopTech was damages were set at a little over $30M. With appeals unsuccessful, ATopTech announced that it has filed a voluntary petition under Chapter 11 of the Bankruptcy Code and has filed a motion to sell its businesses using a stalking horse bidder (an initial b... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 20 Mar, 2015 - Comments: 0

For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above work for Altera. Now, Altera will soon select a foundry partner for 10nm. “Altera will make a decision on which foundry partner it will choose for 10nm finFET at the end of 1Q15, noting it will decide between Intel and TSMC,” said John Vin... » read more

Partition Lines Growing Fuzzy
By Ed Sperling - 26 Feb, 2015 - Comments: 0

For as long as most semiconductor engineers can remember, chips with discrete functions started out on a printed circuit board, progressed into chip sets when it made sense and eventually were integrated onto the same die. The primary motivations behind this trend were performance and cost—shorter distance, fewer mask layers, less silicon. But this equation has been changing over the past ... » read more

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