tag: PDK

Enabling Accurate Electronic-Photonic Co-Design with a Synergetic Workflow on GlobalFoundries Fotonix Platform
By Ansys - 09 Nov, 2022 - Comments: 0

Massive growth in research, development, and applications of CMOS-compatible integrated photonics in recent years, along with its expected potential for the years to come, has sparked an ever-increasing demand from designers for seamless and all-inclusive design automation solutions that can enable electronic-photonic co-design while being accurate and easy to use. Here, we demonstrate an end-t... » read more

How To Create A Physics-Based Laser Compact Model For A Photonic Process Design Kit (PDK)
By Ansys - 11 May, 2022 - Comments: 0

This paper discusses the importance of accurate laser compact models in photonic process design kits, describes different laser models available in Ansys Lumerical INTERCONNECT, and explains optimal steps to create a laser compact model that includes temperature and noise effects. Click here to access the paper. » read more

IP Management And Development At 5/3nm
By Ann Mutschler - 24 Oct, 2019 - Comments: 1

The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

Fast LFD Flows With Pattern Matching And Machine Learning Can Deliver Higher-Yielding Designs Faster
By Wael elManhawy - 22 Aug, 2019 - Comments: 0

By Wael ElManhawy and Joe Kwan A lithographic (litho) hotspot is a defect on a wafer that is created during manufacturing by a combination of systematic process variation and resolution enhancement technology (RET) limitations. Litho hotspots typically represent severe yield detractors, so detecting and eliminating potential litho hotspots prior to manufacturing is crucial to achieving a com... » read more

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Tech Talk: Analog Simplified
By Ed Sperling - 16 Apr, 2018 - Comments: 0

Benjamin Prautsch, Fraunhofer EAS' group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes. https://youtu.be/6ISL1A7Wy_I » read more

Faster Time To Yield
By Ed Sperling - 23 Aug, 2016 - Comments: 2

Michael Jamiolkowski, president and CEO of Coventor, sat down with Semiconductor Engineering to talk about ways improve yield ramp and optimize designs. What follows are excerpts of that conversation. SE: Why does it take so long to get a chip all the way through to manufacturing? Jamiolkowski: There are three parts to that. There is a research side. You want to be able to explore new th... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 05 Jun, 2015 - Comments: 1

In what was called a defensive measure by some, Intel has announced a definitive agreement to acquire Altera for $54 per share in an all-cash transaction valued at approximately $16.7 billion. Here’s what one analyst said about the deal. “We continue to believe Intel’s pursuit of Altera–at a significant premium–was based on a defensive position, rather than the purely accretive str... » read more

One-On-One: Thomas Caulfield
By Mark LaPedus - 21 May, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at [getentity id="22819" comment="GlobalFoundries"]. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion. SE: Last year, GlobalFoundr... » read more

Taming The PDK Beast At DAC
By Steve Schulz - 19 May, 2014 - Comments: 0

A quick Web search on the phrase “process design kit” reveals about 48 million matches. This happens to be about 10 times larger than for the current pop dance sensation “twerking,” so I guess that’s at least something to brag about. Yet if we now add the word interoperability to our PDK search, we find only 200K matches, or less than 0.5% — and therein exposes the chronic problem w... » read more

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