GPU-Based Computing In Photomask Manufacturing

By Aki Fujimura - 28 Mar, 2016 - Comments: 0

Graphical-processing unit (GPU)-accelerated computing has reached maturity for professional, scientific computing applications. One example of this is the recent GPU-accelerated thermal application for semiconductor photomask manufacturing, which is used in 24/7 manufacturing environments. GPU-accelerated computing won’t be a universal panacea for the semiconductor industry’s “need for sp... » read more

Tech Talk: GPU-Accelerated Photomasks

By Ed Sperling - 22 Mar, 2016 - Comments: 0

Noriaki Nakayamada, group manager for the data control engineering group in NuFlare's Mask Lithography engineering Department, talks about what's changing on the mask side, where the trouble spots are, and how to deal with them at advanced process nodes. [youtube vid=f8PixJMadXw] » read more

Multi-Beam Market Heats Up

By Mark LaPedus - 17 Mar, 2016 - Comments: 3

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market. In one surprising move, [getentity id="22846" e_name="Intel"] is in the process of acquiring IMS Nanofabrication, a [gettech id="31058" t_name="multi-beam e-beam"] equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer t... » read more

Ready For Nanoimprint?

By Michael Watts - 17 Mar, 2016 - Comments: 0

Nanoimprint has been discussed, debated, and hyped since the term was first introduced in 1996. Now, a full 20 years later, it is being taken much more seriously in light of increasing photomask costs and delays in bringing alternatives to market. Nanoimprint lithography is something like a room-temperature UV cure embossing process. The structures are patterned onto a template or mold using... » read more

Where Is Next-Gen Lithography?

By Mark LaPedus - 17 Mar, 2016 - Comments: 4

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Greg McIntyre, director of the Advanced Patterning Department at [getentity id="22217" comment="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; Uday Mitra, vice president and head of strategy and marketing for the Etch Bu... » read more

Behind The Scenes In Nanoimprint Lithography

By Jan Willis - 17 Mar, 2016 - Comments: 0

Doug Resnick, VP of marketing and business development at Canon Nanotechnologies, talks about why Canon bought Molecular Imprints, the surprises behind that acquisition, and the problems faced by the semconductor industry moving forward. [youtube vid=NJTxFu-_6GI] » read more

1xnm DRAM Challenges

By Mark LaPedus - 18 Feb, 2016 - Comments: 3

At a recent event, Samsung presented a paper that described how the company plans to extend today’s planar DRAMs down to 20nm and beyond. This is an amazing feat. Until very recently, most engineers believed DRAMs would stop scaling at 20nm or so. Instead, Samsung is ramping up the world’s most advanced DRAMs—a line of 20nm parts—with plans to go even further. Micron and SK Hynix soo... » read more

When And How Should I Color My DP layout?

By David Abercrombie - 18 Feb, 2016 - Comments: 0

Designers working with advanced process technologies that require double patterning often find themselves puzzling over the best way to setup or optimize their design flows to ensure their layouts can be decomposed without time-wasting mistakes. Because manual coloring can be challenging even for experienced engineers, many prefer to use automated coloring solutions. But when is the best time a... » read more

5nm Fab Challenges

By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

Tech Talk: Double-Triple Patterning

By Brian Bailey - 21 Jan, 2016 - Comments: 0

Mentor Graphics' David Abercrombie shows the differences and challenges in double patterning versus triple patterning. [youtube vid= e0wZmjBbEf0] » read more

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tag: photomasks