tag: power delivery

Power Delivery Challenged By Data Center Architectures
By Ann Mutschler - 08 Aug, 2024 - Comments: 0

Processor and data center architectures are changing in response to the higher voltage needs of servers running AI and large language models (LLMs). At one time, servers drew a few hundred watts for operation. But over the past few decades that has changed drastically due to a massive increase in the amount of data that needs to be processed and user demands to do it more quickly. NVIDIA's G... » read more

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 0

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

An Inside Look At Testing’s Leading Edge
By Ed Sperling - 12 May, 2020 - Comments: 0

Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

3D Power Delivery
By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

Executive Briefing: Andrew Yang
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation. LPHP: What’s the most important issue these days for chipmakers? Yang: According to the feedback we’ve gotten from our customer... » read more

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