tag: power

Smaller, Faster, Cheaper—But Different
By Ed Sperling - 22 Mar, 2018 - Comments: 0

The old mantra of "smaller, faster, cheaper" has migrated from the chip level to the electronic system level, raising some interesting questions about where the real value is being generated. Smaller as it pertains to gate size, line widths and spaces, will continue in an almost straight line for at least the next decade. The ability to print three-dimensional features on a nanoscale using E... » read more

In-Design Rail Analysis Is A Beautiful Thing
By Kenneth Chang - 22 Mar, 2018 - Comments: 0

As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which bri... » read more

Why All Nodes Won’t Work
By Ed Sperling - 08 Mar, 2018 - Comments: 4

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

Energy Requirements And Challenges For IoT Autonomous Intelligence At The Edge
By Allen Baker - 08 Mar, 2018 - Comments: 0

Recently, on a cold February night at San Jose State University, I attended the fourth episode of the talk series IR4: The Cognitive Era. IR4 talks focus on the fourth Industrial Revolution that is currently taking place and how cognitive science affects education, careers, and life. This latest part involved four esteemed experts on cloud and edge computing and the ramifications of energy effi... » read more

By the Power Vested in Me, I Now Pronounce You (The SoC Designer)…
By Dave Stratman - 08 Mar, 2018 - Comments: 0

…Doomed. Well, maybe that’s a little harsh, but your job won’t be getting any easier; that “happily ever after” may be harder to achieve than you think, and there are a number of reasons why. And by “me” (of vested power), here I’m really talking about the power of the consumer market as a whole and our collective insatiable demand for newer, shinier…well, just plain “coo... » read more

Low-Power Deep Learning Implementation For Automotive ICs
By Gordon Cooper - 01 Mar, 2018 - Comments: 0

Examples of automotive applications abound where high-performance, low-power embedded vision processors are used, from in-car driver drowsiness detection, to a self-driving car ‘seeing’ the road ahead with pedestrians, oncoming cars, or the occasional animal crossing the road. Implementing deep learning in these types of applications requires a lot of processing power with the lowest possib... » read more

Regain Your Power With Machine Learning
By Shekhar Kapoor - 22 Feb, 2018 - Comments: 0

It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

7/5nm Timing Closure Intensifies
By Ann Mutschler - 25 Jan, 2018 - Comments: 1

Timing closure issues are increasing in magnitude at 7/5nm, and ones that were often considered minor in the past no longer can be ignored. Timing closure is an essential part of any chip design. The process ensures that all combinatorial paths through a design meet the necessary timing so that it can run reliably at a specified clock rate. Timing closure hasn't changed significantly over th... » read more

Methodology For Analyzing And Quantifying Design Style Changes And Complexity Using Topological Patterns
By Cadence - 10 Jan, 2018 - Comments: 0

In order to maximize yield, IC design companies spend a lot of effort to analyze what types of design styles are needed and used in their layouts (standard cells, macros, routing layers, and so forth). This paper introduces a novel methodology for full chip high performance topological pattern analysis and the applications of this methodology towards analyzing design styles in order to quanti... » read more

Advanced Packaging Still Not So Simple
By Ed Sperling - 08 Jan, 2018 - Comments: 1

The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world. There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, wi... » read more

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