tag: probe cards

Promises and Perils of Parallel Test
By Anne Meixner - 10 Sep, 2024 - Comments: 1

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

Test Connections Clean Up With Real-Time Maintenance
By Anne Meixner - 08 Nov, 2022 - Comments: 0

Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Advanced mm-Wave And Terahertz Measurements With Cascade Probe Stations
By FormFactor - 06 Jul, 2021 - Comments: 0

The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

Managing Wafer Retest
By Anne Meixner - 19 May, 2021 - Comments: 1

Every wafer test touch-down requires a balance between a good electrical contact and preventing damage to the wafer and probe card. Done wrong, it can ruin a wafer and the customized probe card and result in poor yield, as well as failures in the field. Achieving this balance requires good wafer probing process procedures as well as monitoring of the resulting process parameters, much of it ... » read more

Digital Test Bulks Up – Or Down
By Bryon Moyer - 08 Dec, 2020 - Comments: 2

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 29 May, 2020 - Comments: 0

Fab tools and test KLA has announced the formation of a new business group for its Electronics, Packaging and Components (EPC) businesses. The new EPC group includes the ICOS, Orbotech and the SPTS Technologies organizations. The group will be headed by Oreste Donzella, KLA’s executive vice president. In 2018, KLA acquired Orbotech for $3.4 billion, a deal that included two organizations-... » read more

An Inside Look At Testing’s Leading Edge
By Ed Sperling - 12 May, 2020 - Comments: 0

Mike Slessor, president and CEO of FormFactor, sat down with Semiconductor Engineering to discuss testing of AI and 5G chips, and why getting power into a chip for testing is becoming more difficult at each new node. SE: How does test change with AI chips, where you've got massive numbers of accelerators and processors developed at 7 and 5nm? Slessor: A lot of the AI stuff that we've been... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 10 Apr, 2020 - Comments: 0

Market research The coronavirus pandemic continues to reduce the outlook for worldwide GDP as well as the electronics and IC markets. For example, IC Insights has lowered its IC forecast from 3% to minus 4% in 2020. The IC market is now expected to hit $345.8 billion in 2020, which is $39.0 billion less than the original forecast, which called for an 8% increase this year. Due to the imp... » read more

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