The Threat Within


By Connie Duncan Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called via... » read more

Flowing Copper


By Richard Lewington If you were to slice up a microchip and take a look (you’d need a really powerful microscope, I'm afraid) you would see what looks like a nanoscale layer cake. All the active circuit elements—transistors, memory cells, etc.—are on the bottom. The other 90% of the chip is a maze of tiny copper wires, which we call interconnects. The history of chip developme... » read more

Capping Tools Tame Electromigration


By Mark LaPedus The shift towards the 28nm node and beyond has put the spotlight back on the interconnect in semiconductor manufacturing. In chip scaling, the big problem in the interconnect is resistance-capacitance (RC). Another, and sometimes forgotten, issue is electromigration. “Electromigration gets worse in device scaling,” said Daniel Edelstein, an IBM Fellow and manager of BE... » read more

Challenges Mount For Interconnect


By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

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