Surprises At SEMICON West


As companies such as TSMC and Intel spend less on capital expenditures this year, expectations for SEMICON West 2015 were pretty bleak. I thought I’d have fewer appointments and nothing to really write home about. Au contraire. Although traffic on the show floor was nothing compared to events like CES, there are three things that are driving growth and excitement at semiconductor equipment... » read more

Extending The Hardmask


In chip production, the backend-of-the-line (BEOL) is where the critical interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips. “The scaling roadblocks that the interconnect faces need to ... » read more

Will 7nm And 5nm Really Happen?


Today’s silicon-based finFETs could run out of steam at 10nm. If or when chipmakers move beyond 10nm, IC vendors will require a new transistor architecture. III-V finFETs, gate-all-around FETs, quantum well finFETs, SOI finFETs and vertical nanowires are just a few of the future transistor candidates at 7nm and 5nm. Technically, it’s possible to manufacture the transistor portions of the... » read more

Interconnect Challenges Grow


Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

Manufacturing Bits: July 16


Photon Chips Harvard University, the Massachusetts Institute of Technology (MIT) and the Vienna University of Technology have devised an all-optical transistor controlled by a single photon. The optical transistor could enable the development of photonic quantum gates and deterministic multi-photon entanglement. For years, researchers have been looking to develop an optical transistor, whe... » read more

Trickle Down Equipment Economics


By Jeff Chappell By now, with the rise of China as a center of manufacturing, everyone in the chip industry has no doubt heard of the supposed Chinese curse, "May you live in interesting times." It's practically cliché. The thing is, the next two industry cycles may indeed prove interesting for the used equipment market. At the moment, everyone is tired of interesting times, and those in ... » read more

The Threat Within


By Connie Duncan Given that today’s advanced chips can contain billions of transistors, 60 miles of copper wiring and 10 billion vertical connections between metal layers, the challenges and potential pitfalls this level of complexity presents are mind-boggling. One major problem on the horizon at 20nm and below is the threat of voids forming in the vertical interconnects commonly called via... » read more

Flowing Copper


By Richard Lewington If you were to slice up a microchip and take a look (you’d need a really powerful microscope, I'm afraid) you would see what looks like a nanoscale layer cake. All the active circuit elements—transistors, memory cells, etc.—are on the bottom. The other 90% of the chip is a maze of tiny copper wires, which we call interconnects. The history of chip developme... » read more

Capping Tools Tame Electromigration


By Mark LaPedus The shift towards the 28nm node and beyond has put the spotlight back on the interconnect in semiconductor manufacturing. In chip scaling, the big problem in the interconnect is resistance-capacitance (RC). Another, and sometimes forgotten, issue is electromigration. “Electromigration gets worse in device scaling,” said Daniel Edelstein, an IBM Fellow and manager of BE... » read more

Challenges Mount For Interconnect


By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more

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