TSVs Ease Heat In 3D ICs


By Ann Steffora Mutschler In the evolving discussion of 3D ICs and through silicon via (TSV) technology, a key issue engineering teams are facing today is how to reduce the thermal coefficients between substrates in a stacked die. Simply put, what is the best way to get the heat out of the 2.5 or 3D IC? The answer, of course, is anything but simple. “In a 3D system, the heat hierarchy ... » read more

Dueling Power Formats


By Ed Sperling Multiple power formats and increasingly complex SoCs don’t sound like a winning formula. So just how bad have things become? Low-Power Engineering asked Sorin Dobre, senior staff engineer at Qualcomm, for a real-world assessment of the situation. LPE: There are three power formats—CPF, UPF and IEEE 1801. How big a problem is this for Qualcomm? Dobre: Actually we have CPF... » read more

Next Up: Touchless Screens


By Kurt Shuler Gesture Recognition Qualcomm’s announcement this Monday that it has acquired assets from gesture recognition technology pioneer GestureTek makes it official: Gesture recognition based on video camera technology will be in phones sooner than we think. [caption id="attachment_7583" align="alignnone" width="716"] Source: TI and YouTube[/caption] Video-based gesture recognit... » read more

Keeping Up With Complexity


By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

Widening The Channels


By Ed Sperling Wide I/O—both as a specific memory standard and as a generic approach for on-chip networking—has been looked at for the past couple of chip generations as a way of improving SoC performance. Increasingly, it also is being used as a key strategy for reducing energy consumption. Wide I/O refers to a number of different approaches in on-chip networking, ranging from through-... » read more

Experts At The Table: 3D Stacking


By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pr... » read more

Experts At The Table: 3D Stacking


By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pr... » read more

Experts At The Table: 3D Stacking


By Ed Sperling Semiconductor Manufacturing and Design sat down with Riko Radojcic, director of engineering at Qualcomm; Drew Wingard, CTO at Sonics; Michael White, senior product marketing manager for Calibre physical verification at Mentor Graphics; Jim Hogan, a Silicon Valley venture capitalist; Prasad Subramaniam, vice president of design technology at eSilicon; and Mike Gianfagna, vice pre... » read more

Power Management Trumps Battery Technology


By Ann Steffora Mutschler The lithium-ion battery has the power to ruin someone’s day, especially when it dies and cannot be charged, not to mention occasional thermal runaways that literally cause explosions. For a technology that is about 30 years old, and approaching its limits, it is mind-boggling that the best brains on the planet haven’t come up with a technological superior alternat... » read more

Qualcomm Shies Away From High-k At 28nm


By David Lammers Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28 nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy, which because of Qualcomm’s size will have a major impact on the foundry business, at the 2010 International Electron Devices Meeting (IEDM) held in ... » read more

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