tag: Qualcomm

Making Too Much Noise
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ed Sperling For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change. Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signal... » read more

EUV Focus Shifts To Affordability
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By David Lammers Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, ... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

New Forces For Consolidation
By Ed Sperling - 05 Mar, 2010 - Comments: 0

For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single... » read more

Low-Power Architectures Go Mainstream
By Pallab Chatterjee - 14 Jan, 2010 - Comments: 0

By Pallab Chatterjee Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology. There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions fr... » read more

Following The WLAN Alphabet To Lower Power
By Ed Sperling - 20 Aug, 2009 - Comments: 0

By Cheryl Ajluni The quest for low power in electronic devices is one that shows no sign of abating any time soon. Pressure for it comes from many different sources, such as the continual drive to pack more functionality into ever smaller, mobile electronic devices. To try and maintain a decent battery life for today’s power-hungry “road-warriors,” engineers have to reduce power con... » read more

Who’s In Control Now?
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

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