tag: Rambus

Week In Review: Design, Low Power
By Jesse Allen - 13 Dec, 2019 - Comments: 0

Rambus finalized its acquisition of the silicon IP, secure protocols and provisioning business from Verimatrix, formerly Inside Secure, for $45 million at closing, and up to an additional $20 million, subject to certain revenue targets in 2020. RISC-V SiFive unveiled two new product families. The SiFive Apex processor cores target mission-critical processors with Size, Weight, and Power (SW... » read more

Taking A Closer Look At Side Channel Attacks
By Gary Kenworthy - 05 Dec, 2019 - Comments: 0

In last month’s Semiconductor Engineering article, we explored the basics of side channel attacks (SCAs). As we discussed, all cryptographic algorithms are subject to side channel attacks, with vulnerabilities extending across all platforms and form factors. In this article, we’ll be taking a closer look at the two primary categories of side channel attacks: simple power analysis (SPA) and ... » read more

A Trillion Security Risks
By Yuri Nagano - 05 Dec, 2019 - Comments: 0

An explosion in IoT devices has significantly raised the security threat level for hardware and software, and it shows no sign of abating anytime soon. Sometime over the next decade the number of connected devices is expected to hit the 1 trillion mark. Expecting all of them to be secure is impossible, particularly as the attack surface widens and the attack vectors become more sophisticated... » read more

Analysis, Modeling And Characterization Of Multi-Protocol High-Speed Serial Links
By Rambus - 04 Dec, 2019 - Comments: 0

Improved analysis, modeling, characterization and correlation methods of multi-protocol high-speed transceivers that utilize T-coil to enhance the transmitter and receiver bandwidth, transmitter FIR filters and receiver CTLE and DFE equalizers is presented. The key circuit blocks are measured and modeled using IBIS-AMI models and the overall system performance including the eye diagrams, BER cu... » read more

Blog Review: Nov. 27
By Jesse Allen - 27 Nov, 2019 - Comments: 0

Arm's Ben Fletcher digs into what's needed to make wireless 3D integration a reality from a tool to automate the design and optimization process for inductors used in wireless 3D-ICs to exploring how the data can be encoded in the transceiver to reduce power consumption. Cadence's Paul McLellan listens in as Eli Singerman of Intel explains the importance of platform security and why firmware... » read more

Why Standard Memory Choices Are So Confusing
By Ann Mutschler - 19 Nov, 2019 - Comments: 0

System architects increasingly are developing custom memory architectures based upon specific use cases, adding to the complexity of the design process even though the basic memory building blocks have been around for more than half a century. The number of tradeoffs has skyrocketed along with the volume of data. Memory bandwidth is now a gating factor for applications, and traditional memor... » read more

RISC-V Markets, Security And Growth Prospects
By Ed Sperling - 18 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss open instruction set hardware with Ben Levine, senior director of product management in Rambus' Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.  Part one of this discussion is ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 15 Nov, 2019 - Comments: 0

M&A eSilicon will be acquired by Inphi Corporation and Synopsys. Inphi is acquiring the majority of the company, including the ASIC business and 56/112G SerDes design and related IP, for $216 million in both cash and the assumption of debt. Inphi expects to combine its DSP, TiA, Driver and SiPho products with eSilicon’s 2.5D packaging and custom silicon design capabilities for electro-optics... » read more

Week in Review: IoT, Security, Automotive
By SE Staff - 15 Nov, 2019 - Comments: 0

Connectivity, 5G Rambus has revealed a PCI Express 5.0 interface on advanced 7nm finFET process node for heterogenous computing aimed at performance-intensive uses, such as AI, data center, HPC, storage and 400GbE networking. With a PHY and a digital controller core recently acquired Northwest Logic, the interface has 32 GT/s (gigatransfers per second) bandwidth per lane with 128 GB/s bandwidt... » read more

GDDR6 Drilldown: Applications, Tradeoffs And Specs
By Ed Sperling - 15 Nov, 2019 - Comments: 0

Frank Ferro, senior director of product marketing for IP cores at Rambus, drills down on tradeoffs in choosing different DRAM versions, where GDDR6 fits into designs versus other types of DRAM, and how different memories are used in different vertical markets. » read more

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