tag: RDL

Manual X-ray Inspection
By Ed Sperling - 28 Aug, 2023 - Comments: 0

Increased density in advanced node chips and advanced packaging offers a way to greatly improve performance and reduce power, but it also makes it harder to inspect these devices for real and latent defects. Higher density can lead to scattering of light, and heterogeneous integration in a package means it’s not always possible to see through all materials equally. Chris Rand, product line ma... » read more

A Hybrid PLP Technology Based On A 650mm x 650mm Platform
By Eoin O'Toole - 25 Jul, 2023 - Comments: 0

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package di... » read more

Addressing Copper Clad Laminate Processing Distortion Using Overlay Corrections
By Keith Best - 11 Jul, 2023 - Comments: 0

All great voyages must come to an end. Such is the case with our series on the challenges facing the manufacturing of advanced IC substrates (AICS), the glue holding the heterogeneous integration ship together. In our first blog, we examined how cumulative overlay drift from individual redistribution layers could significantly increase overall trace length, resulting in higher interconnect res... » read more

High-Density Fan-Out Packaging With Fine Pitch Embedded Trace RDL
By WonChul Do - 15 Jun, 2023 - Comments: 0

The needs of high-performance devices for artificial intelligence (AI), high performance computing (HPC) and data center applications have drastically accelerated during the Covid-19 pandemic period. At the same time, the integrated circuit (IC) industry struggles to minimize the silicon technology node to satisfy the endless requirements of computing performance within tight cost constraints. ... » read more

Addressing Total Overlay Drift In Advanced IC Substrate (AICS) Packaging
By Keith Best - 07 Mar, 2023 - Comments: 0

For years, many in the semiconductor industry have focused on the march toward advanced nodes. As these nodes have decreased in size, the size of input/output (I/O) bumps on the chip has grown smaller. As these bumps shrink, their ability to mate directly to printed circuit boards (PCB) diminishes, which, in turn, leads to the need for an intermediary substrate. Enter the advanced IC substrate ... » read more

The Path To Known Good Interconnects
By Laura Peters - 19 Jan, 2023 - Comments: 1

Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Improving Redistribution Layers for Fan-out Packages And SiPs
By Laura Peters - 15 Sep, 2022 - Comments: 2

Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

Fan-Out Packaging Gets Competitive
By Karen Heyman and Laura Peters - 18 Aug, 2022 - Comments: 0

Fan-out wafer-level packaging (FOWLP) is a key enabler in the industry shift from transistor scaling to system scaling and integration. The design fans out the chip interconnects through a redistribution layer instead of a substrate. Compared to flip-chip ball grid array (FCBGA) or wire bonds, it creates lower thermal resistance, a slimmer package, and potentially lower costs. Yet, if the h... » read more

Study Of Bondable Laser Release Material Using 355nm Energy To Facilitate RDL-First And Die-First Fan-Out Wafer-Level Packaging (FOWLP)
By Brewer Science - 18 May, 2022 - Comments: 0

A thorough evaluation on selecting a bondable laser release material for redistribution layer (RDL)-first and die-first fan-out wafer-level packaging (FOWLP) is presented in this article. Four laser release materials were identified based on their absorption coefficient at 355 nm. In addition, all four of these materials possess thermal stability above 350 °C and pull-off adhesion on a Ti/Cu l... » read more

Big Changes In Materials And Processes For IC Manufacturing
By Ed Sperling And Laura Peters - 21 Apr, 2022 - Comments: 3

Rama Puligadda, CTO at Brewer Science, sat down with Semiconductor Engineering to talk about a broad set of changes in semiconductor manufacturing, packaging, and materials, and how that will affect reliability, processes, and equipment across the supply chain. SE: What role do sacrificial materials play in semiconductor manufacturing, and how is that changing at new process nodes? Puliga... » read more

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