Chip Design Digs Deeper Into AI

By Ann Mutschler - 03 Jun, 2024 - Comments: 0

Growing demand for blazing fast and extremely dense multi-chiplet systems are pushing chip design deeper into AI, which increasingly is viewed as the best solution for sifting through scores of possible configurations, constraints, and variables in the least amount of time. This shift has broad implications for the future of chip design. In the past, collaborations typically involved the chi... » read more

The Future Of Fault Coverage In Chips

By Gregory Haley - 14 May, 2024 - Comments: 0

Heterogeneous integration and sophisticated packaging are making chips more difficult to test, necessitating more versatile and efficient testing methods to minimize the time and cost it takes for each test insertion. In the past, test costs typically were limited to about 2% of the total cost of a chip. That cost has been rising in recent years, and with chiplets, advanced packaging, and mo... » read more

Electromigration Concerns Grow In Advanced Packages

By Laura Peters - 18 Apr, 2024 - Comments: 0

The incessant demand for more speed in chips requires forcing more energy through ever-smaller devices, increasing current density and threatening long-term chip reliability. While this problem is well understood, it's becoming more difficult to contain in leading-edge designs. Of particular concern is electromigration, which is becoming more troublesome in advanced packages with multiple ch... » read more

IC Test And Quality Requirements Drive New Collaboration

By Laura Peters - 09 Apr, 2024 - Comments: 0

Rapidly increasing chip and package complexity, coupled with an incessant demand for more reliability, has triggered a frenzy of alliances and working relationships that are starting to redefine how chips are tested and monitored. At the core of this shift is a growing recognition that no company can do everything, and that to work together will require much tighter integration of flows, met... » read more

Early Cycle Analysis And Verification Of Logical SEU Mitigation

By Jacob Wiltgen - 04 Apr, 2024 - Comments: 0

The global appetite for data continues to soar, driving innovation across all industry sectors, including how space-based technology can facilitate a more connected world. Miniaturized satellites configured into constellations offer faster communication and higher bandwidth than lone satellites flying higher in geocentric or high-earth orbits. However, industry analysis suggests that to make... » read more

Cost And Quality Of Chiplets

By Ed Sperling - 19 Mar, 2024 - Comments: 0

Chiplets add a whole new challenge for the semiconductor industry. How much testing is enough? How do you optimize system binning? What’s the right amount of burn-in? The answers to these questions will vary, depending upon cost and quality tradeoffs, the number and source of the chiplets, and real-world workloads and projected lifespans. Marc Jacobs, senior director of solutions architectur... » read more

Silent Data Corruption Considerations For Advanced Node Designs

By Jyotika Athavale - 12 Mar, 2024 - Comments: 0

Ensuring reliability, availability, and serviceability (RAS) has long been an important consideration for many types of electronic systems, with major implications for chip design. Clearly, military hardware must be very reliable, and servers and automotive systems are also expected to be available constantly. Some amount of failure is inevitable, so being able to repair, avoid, or mitigate fau... » read more

V2X Path To Deployment Still Murky

By Ann Mutschler - 07 Mar, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss Vehicle-To-Everything (V2X) technology and the path to deployment, with Shawn Carpenter, program director for 5G and space at Ansys; Lang Lin, principal product manager at Ansys; Daniel Dalpiaz, senior manager product marketing, Americas, green industrial power division at Infineon; David Fritz, vice president of virtual and hy... » read more

Memory’s Future Hinges On Reliability

By Karen Heyman - 14 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of power and heat on off-chip memory, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

Adaptive Test Ramps For Data Intelligence Era

By Laura Peters - 08 Feb, 2024 - Comments: 0

Widely available and nearly unlimited compute resources, coupled with the availability of sophisticated algorithms, are opening the door to adaptive testing. But the speed at which this testing approach is adopted will continue to vary due to persistent concerns about data sharing and the potential for IP theft and data leakage. Adaptive testing is all about making timely changes to a test p... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: reliability