Using Deep Data Analytics To Enhance Reliability Testing The Fast Roadmap for Zero Defects


proteanTecs and ELES have partnered together to enhance reliability testing with deep data analytics. This collaboration enables SoC manufacturers to improve their qualification envelope to achieve lifetime reliability, shorten their root cause analysis time, and reduce operational costs. This innovative approach adds parametric measurements during the stress test in order to accurately and pre... » read more

Making Sensors More Reliable


Experts at the Table: Semiconductor Engineering sat down to talk about the latest issues in sensors with Prakash Madhvapathy, director of product marketing, Tensilica audio/voice DSPs group at Cadence; Kevin Hughes, senior product manager for MEMS sensors at Infineon; and Matthew Hogan, product management director at Siemens EDA. What follows are excerpts of that conversation. [L-R] Kevin ... » read more

Data, System Reliability, and Privacy


Experts at the Table: Semiconductor Engineering sat down to discuss changes in test that address tracing device quality throughout a product’s lifetime, and over-arching concerns about data ownership and privacy, with Tom Katsioulas, CEO at Archon Design Solutions and U.S. Department of Commerce IoT advisory board member; Ming Zhang, vice president of R&D Acceleration at PDF Solutions; a... » read more

Challenges Of Testing Advanced Packages


The number of things that can wrong in assembly and test increases as more chips are added into a package. Testing is the usual guarantor of a reliable device, but in an advanced package there are all sorts of new issues — more contacts, different handling requirements, the necessary thermal conditions for test, and variation within the package. George Harris, vice president of global test se... » read more

Reliability On The Rise In IC Design


Reliability has been an important factor in the semiconductor industry for decades. A closer look reveals three main priorities: In the area of technology development and optimization, the microscopic mechanisms that lead to degradation must be identified and understood before they can be fixed. Microanalytical methods are used here as well as TCAD simulations. If it’s not possible to... » read more

Customizing IC Test To Improve Yield And Reliability


Testing the performance and power of semiconductors as they come off the production line is beginning to shift left in the fab, reversing a long-standing trend of assessing chips just prior to shipping. While this may sound straightforward, it's a difficult challenge which, if successful, will have broad implications for the entire design-through-manufacturing flow. Manufacturers typically g... » read more

Automotive Safety Requires PVT Monitoring IP Within Semiconductor ICs


The modern automobile, especially with the move toward more electrification, presents huge challenges to the designers of vehicular electronics. Gone are the days of mechanical issues and oil changes being primary concerns. Today’s automobile has a high number of semiconductor chips performing functions for self-driving autonomous systems, advanced driver assistance systems (ADAS), connectivi... » read more

Shift Left, Extend Right, Stretch Sideways


The EDA industry has been talking about shift left for a few years, but development flows are now being stretched in two additional ways, extending right to include silicon lifecycle management, and sideways to include safety and security. In addition, safety and security join verification and power as being vertical concerns, and we are increasingly seeing interlinking within those concerns. ... » read more

Mitigating Electromigration In Chip Design


From smartphones to laptops, we use a variety of devices every day that rely on integrated circuits (ICs), or chips, to function. These chips are made up of thousands of transistors and interconnects, which transmit electrical signals from one part of the chip to another. But as demand for speed and complexity forces more energy through ever-smaller devices, this concentrated current flow can t... » read more

RowPress: Read-Disturb Phenomenon In DDR4 DRAM Chips


A technical paper titled "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" was published by researchers at ETH Zürich. Abstract: "Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and clo... » read more

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