tag: RISC-V

Verification In The Open Source Era
By Brian Bailey - 25 Mar, 2021 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down to discuss what open source verification means today and what it should evolve into, with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Ashish Darbari, CEO of Axiomise; Simon Davidmann, CEO of Imperas Software; Serge Leef, program manager in the Microsystems Technology Office at DARPA; Tao Liu, staff hardwa... » read more

A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing
By Codasip - 24 Mar, 2021 - Comments: 0

This work presents an instruction-set extension to the open-source RISC-V ISA (RV32IM) dedicated to ultra-low power (ULP) software-defined wireless IoT transceivers. The custom instructions are tailored to the needs of 8/16/32-bit integer complex arithmetic typically required by quadrature modulations. The proposed extension occupies only 2 major opcodes and most instructions are designed to co... » read more

An Insider’s View Of Verifying Custom RISC-V Processor Cores
By Shubhodeep Roy Choudhury - 15 Mar, 2021 - Comments: 0

By Shubhodeep Roy Choudhury, Valtrix Systems, and Lee Moore, Imperas Software Supporting images courtesy of Bill McSpadden, Seagate Technology This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V proce... » read more

The Single Greatest Opportunity For Open Source
By Brian Bailey - 25 Feb, 2021 - Comments: 7

Next week, I will be moderating a panel at the virtual DVCon on the subject of open-source verification. I thought it would be good to advertise the event on LinkedIn to see if anyone wanted to send me well-structured questions for the panelists. What happened surprised me a little because the discussions almost exclusively went to the need for open-source verification tools. In my opinion, the... » read more

Customizing An Existing RISC-V Processor
By Roddy Urquhart - 25 Feb, 2021 - Comments: 0

In a previous post, we considered how you could create an optimized ISA for a domain-specific processor core by profiling software and experimenting with adding/removing instructions. Using the open RISC-V ISA can be a great starting point for a processor that combines application-specific capabilities and access to portable software. The old-fashioned way to modify the instruction set wo... » read more

The Problem With Benchmarks
By Brian Bailey - 11 Feb, 2021 - Comments: 1

Benchmarks long have been used to compare products, but what makes a good benchmark and who should be trusted with their creation? The answer to those questions is more difficult than it may appear on the surface, and some benchmarks are being used in surprising ways. Everyone loves a simple, clear benchmark, but that is only possible when the selection criteria are equally simple. Unfortuna... » read more

Big Changes In Verification
By Ann Mutschler - 28 Jan, 2021 - Comments: 0

Verification is undergoing fundamental change as chips become increasingly complex, heterogeneous, and integrated into larger systems. Tools, methodologies, and the mindset of verification engineers themselves are all shifting to adapt to these new designs, although with so many moving pieces this isn't always so easy to comprehend. Ferreting out bugs in a design now requires a multi-faceted... » read more

ISA Ownership Matters: A Tale of Three ISAs
By Roddy Urquhart - 28 Jan, 2021 - Comments: 0

An instruction set architecture (ISA) is crucial to the development of processors and their software ecosystems. In the last half century, the majority of ISAs have been owned by single companies, whether product companies for their own chips/systems or processor IP companies who licensed their processors to chip developers. Does ISA ownership matter? Let’s consider three proprietary ISAs a... » read more

RISC-V Becoming Less Risky With The Right Verification
By Rob van Blommestein - 25 Jan, 2021 - Comments: 1

RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the ... » read more

Verification’s Inflection Point
By Brian Bailey - 14 Jan, 2021 - Comments: 0

Functional verification is nearing an inflection point, brought on by rising complexity and the many tentacles that are intermixing it with other disciplines. New abstractions or different ways to approach the problems are needed. Being a verification engineer is no longer enough, except for those whose concerns is block-level verification. Most of the time and effort spent in verification i... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy