More Than Moore At iMAPS

By Paul McLellan - 02 Dec, 2021 - Comments: 0

San Diego recently hosted the 54th International Symposium on Microelectronics. That's a very generic title, so you should know that it is run by iMAPS, the International Microelectronics Assembly and Packaging Society. Generally, the conference is just known as iMAPS. One of the keynotes was given by Cadence's KT Moore (in person). His presentation was titled "More Moore or More than Moore: a... » read more

What’s Next For Transistors And Chiplets

By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Time To Rethink Memory Chip Design And Verification

By Anand Thiruvengadam - 12 Aug, 2021 - Comments: 1

It’s no secret to anyone that semiconductor development grows more challenging all the time. Each new process technology node packs more transistors into each die, creating more electrical issues and making heat dissipation harder. Floorplanning, logic synthesis, place and route, timing analysis, electrical analysis, and functional verification stretch electronic design automation (EDA) tools... » read more

An Introduction To Domain-Specific Accelerators

By Roddy Urquhart - 24 Jun, 2021 - Comments: 0

After 50 years, Moore’s Law, Dennard Scaling, and Amdahl’s Law are failing. The semiconductor industry much change, and processor paradigms must change with it. So what exactly are domain-specific accelerators and why are they so important in light of the failure of these semiconductor scaling laws? » read more

Bumps Vs. Hybrid Bonding For Advanced Packaging

By Mark LaPedus - 23 Jun, 2021 - Comments: 3

Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding. The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced pac... » read more

The Road To Domain-Specific Accelerators

By Roddy Urquhart - 27 May, 2021 - Comments: 0

For about fifty years, IC designers have been relying on different types of semiconductor scaling to achieve gains in performance. Best known is Moore’s Law, which predicted that the number of transistors in a given silicon area and clock frequency would double every two years. This was combined with Dennard scaling, which predicted that with silicon geometries and supply voltages shrinki... » read more

The Future Of Transistors And IC Architectures

By Mark LaPedus - 18 Mar, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpt... » read more

Die-To-Die Chiplet Communication

By Paul McLellan - 11 Mar, 2021 - Comments: 0

At CadenceLIVE Americas 2020, one of the most viewed videos was by Samsung Foundry's Kevin Yee and Cadence's Tom Wong, titled "Let’s Talk About Chips (Chiplets), Baby…It’s All About D2D!" They went for this title because it reminded them of the lyrics of an '80s song...which they proceeded to sing. Process and packaging trends Tom led off with a look at the trends in semiconducto... » read more

Changing The Rules For Chip Scaling

By Ed Sperling - 10 Mar, 2021 - Comments: 0

Aki Fujimura, CEO of D2S, talks with Semiconductor Engineering about the incessant drive for chip density, how to improve that density through other means than just scaling, and why this is so important for the chip industry. » read more

Imec’s Plan For Continued Scaling

By Paul McLellan - 14 Jan, 2021 - Comments: 0

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world sinc... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: scaling

More Than Moore At iMAPS

What’s Next For Transistors And Chiplets

Time To Rethink Memory Chip Design And Verification

An Introduction To Domain-Specific Accelerators

Bumps Vs. Hybrid Bonding For Advanced Packaging

The Road To Domain-Specific Accelerators

The Future Of Transistors And IC Architectures

Die-To-Die Chiplet Communication

Changing The Rules For Chip Scaling

Imec’s Plan For Continued Scaling

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers
Entities, people and technologies explored