tag: Sematech

Getting Ready For High-Mobility FinFETs
By Mark LaPedus - 21 Feb, 2013 - Comments: 0

By Mark LaPedus The IC industry entered the finFET era in 2011, when Intel leapfrogged the competition and rolled out the newfangled transistor technology at the 22nm node. Intel hopes to ramp up its second-generation finFET devices at 14nm by year’s end, with plans to debut its 11nm technology by 2015. Hoping to close the gap with Intel, silicon foundries are accelerating their efforts t... » read more

There’s More To EUV Than Source Power
By Katherine Derbyshire - 20 Sep, 2012 - Comments: 0

By Katherine Derbyshire For some time now, most industry coverage of EUV lithography has focused on the light source. As my colleagues have pointed out, source power limitations impose major constraints on not only potential EUV-based device manufacturing, but even on development of sub-20nm devices and process technologies. When throughput is in the neighborhood of four wafers per hour, lear... » read more

3D Standards For The Real World
By Ed Sperling - 23 Feb, 2012 - Comments: 0

By Pallab Chatterjee Stacking die has progressed from what is technologically possible to what will be realistically feasible in a fabless or fab-lite world. The big challenges may be less about how to deal with stress caused by a TSV or thermal density and more about companies working together in a disaggregated supply chain. This was quite evident at a recent DesignCon panel dicussion on ... » read more

For want of an o-ring, the mask was lost
By Katherine Derbyshire - 25 Jul, 2011 - Comments: 0

O-ring seals are everywhere in a typical semiconductor fab. Any piece of vacuum equipment uses several of them to seal the openings where components of the process chamber fit together. Yet, as ubiquitous as they are, most process engineers don’t think about them very much. They buy the seal specified by the equipment vendor, from the supplier with the most attractive price, and pretty much l... » read more

The Shape Of Things To Come
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

EUV Focus Shifts To Affordability
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By David Lammers Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, ... » read more

Stressing Over 3D
By Ed Sperling - 24 Jun, 2010 - Comments: 0

By David Lammers Pol Marchal recalls putting a stacked 3D prototype on his desk at IMEC in Leuven, Belgium, last year, which a visitor picked up and examined two months later. “I don’t think this chip will work,” the visitor said, causing Marchal, principal scientist at IMEC’s 3D system integration program, to put the stacked die under a microscope. Sure enough, Pol found that mechanic... » read more

Changing Opinions About Noise
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Brian Fuller On a sunny, warm May day in 2009, NIST researcher Jason Campbell took the stage at an IEEE event in Austin with a presentation that was sure cast a pall over the booming low-power semiconductor world. Campbell’s paper, written with Liangchun Yu, Kin Cheung, Jin Qin, John S. Suehle, A. Oates, Kuang Sheng, was entitled “Large Random Telegraph Noise in Sub-Threshold Opera... » read more

3D Integration: Extending Moore’s Law Into The Next Decade
By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

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