Blog Review: December 13


Synopsys' Charles Dittmer discusses key and emerging use cases for Bluetooth Low Energy and how combining BLE with other wireless protocols can open new avenues of functionality for application areas including automotive, hearables, and retail. Cadence's Neelabh Singh points out changes in the terminologies describing USB4 links and shows the various possible link configurations put forth by... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

Blog Review: November 29


Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

IC Manufacturing Targets Less Water, Less Waste


Fabs, OSATs, and equipment makers are accelerating their efforts to consume less water while recycling more material waste in a trend toward better sustainability. With chips, sustainability is heavily focused on carbon emissions, and energy consumption is a significant contributor. But there is an equal effort underway to reduce water consumption and pollution. Across the globe, the number ... » read more

Maximizing Edge Intelligence Requires More Than Computing


By Toshi Nishida, Avik W. Ghosh, Swaminathan Rajaraman, and Mircea Stan Commercial-off-the-shelf (COTS) components have enabled a commodity market for Wi-Fi-connected appliances, consumer products, infrastructure, manufacturing, vehicles, and wearables. However, the vast majority of connected systems today are deployed at the edge of the network, near the end user or end application, opening... » read more

Blog Review: November 15


Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

Blog Review: Nov. 8


Siemens' Todd Westerhoff takes a look at the three stages of power integrity analysis for PCBs, challenges to board-level signal integrity, and best practices for getting the most accurate estimate of design performance. Synopsys' William Ruby provides a brief overview of the evolution of low-power design techniques and finds opportunities to reduce power and to make chip designs more energy... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Blog Review: November 1


Cadence’s Rich Chang finds that although UVM has being used for testbench creation for more than a decade, it is still challenging to debug problems that are inside of UVM testbench. Siemens’ Keith Felton suggests that early analysis in complex advanced packaging flows can enable designers to spot potential issues early to avoid built-in constructs that cause design failures and require ... » read more

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