tag: SerDes

Long And Longer Reach SerDes – On The Road Again
By Mike Gianfagna - 26 Sep, 2019 - Comments: 0

We’ve had the pleasure of participating in two events over the past two weeks. I wouldn’t recommend doing two major shows back-to-back, but it has been exhilarating and quite interesting. Our “road trip” began last week in Mountain View for the second annual AI Hardware Summit. You’ve probably noticed you can go to an AI-related show every week (or more) if you like. The trick is to f... » read more

Nvidia’s Top Technologists Discuss The Future Of GPUs
By SE Staff - 10 Sep, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the role of the GPU in artificial intelligence, autonomous and assisted driving, advanced packaging and heterogeneous architectures with Bill Dally, Nvidia’s chief scientist, and Jonah Alben, senior vice president of Nvidia’s GPU engineering, at IEEE’s Hot Chips 2019 conference. What follows are excerpts of that conversation. SE: There are ... » read more

OIF Eyes Expanded Electrical Link Definitions For 112 Gbps
By Saman Sadr - 12 Aug, 2019 - Comments: 0

The insatiable demand for more bandwidth, lower latencies, and higher speeds is driven by a diverse range of applications and use cases. These include artificial intelligence /machine learning, sophisticated ADAS systems for semi-autonomous vehicles, 4K-8K video streaming, eSports, and AR/VR. With global IP traffic now measured in zettabytes (ZB) per year, hyperscalers and service providers ... » read more

Meeting The Demands Of PAM4 Systems At 56Gbps And Beyond
By eSilicon - 24 Jul, 2019 - Comments: 0

According to an IDC white paper sponsored by Seagate the global datasphere will grow from 33 zettabytes (one zettabye = one trillion gigabytes) in 2018 to 175 zettabytes by 2025. This white paper also reports that today, more than 5 billion consumers interact with data every day. By 2025, that number will be 6 billion, or 75 percent of the world’s population. Figure 1 depicts this exponential... » read more

Advanced Features Of High Speed Digital I/O Devices: Double Data Rate
By NI - 08 Jul, 2019 - Comments: 0

As clock speeds and data rates continue to increase, designers of digital integrated circuits are creating new ways to maximize the rate of data being sent into and out of digital devices. One such method is known as double data rate (DDR). With single data rate (SDR) devices, data is latched on either the rising or falling edges of the sample clock. A DDR device latches data on both the rising... » read more

CEO Outlook: Rising Costs, Chiplets, And A Trade War
By Ed Sperling - 26 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Wrestling With High-Speed SerDes
By Ann Mutschler - 19 Jun, 2019 - Comments: 2

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

Delivering High-Speed Communications: The Back Story
By Mike Gianfagna - 30 May, 2019 - Comments: 0

Back in January, I posted a blog about what it takes to deliver high-speed communication. In that post, I talked about a new test board for our high-speed 7nm 56G PAM4 & NRZ DSP-based long-reach SerDes. We collaborated with several companies to build a high-precision board that could be used to test our SerDes in a system context. At that time, we were just finishing the opening act for thi... » read more

112G XSR And LR SerDes PHYs
By Rambus - 01 May, 2019 - Comments: 0

The virtuous cycle of increased computing power enabling new applications which demand more computing power continues unabated. Today, applications spanning AI, autonomous vehicles, video streaming, AR and VR all demand more bandwidth, lower latencies and higher speeds. In response, the SoCs powering the terabit routers and switches at the heart of the network must run even faster. The upgrade ... » read more

Moore’s Law Now Requires Advanced Packaging
By Ed Sperling - 18 Apr, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with Calvin Cheung, vice president of engineering at ASE; Walter Ng, vice president of business management at UMC; Ajay Lalwani, vice president of global manufacturing operations at eSilicon; Vic Kulkarni, vice president and chief strategist in the office of the CTO at ANSYS; and Tien Shiah, senior manager for memory at Samsung. W... » read more

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