Early Cycle Analysis And Verification Of Logical SEU Mitigation


The global appetite for data continues to soar, driving innovation across all industry sectors, including how space-based technology can facilitate a more connected world. Miniaturized satellites configured into constellations offer faster communication and higher bandwidth than lone satellites flying higher in geocentric or high-earth orbits. However, industry analysis suggests that to make... » read more

Data Center Security Issues Widen


The total amount of data will swell to about 200 zettabytes of data next year, much of it stored in massive data centers scattered across the globe that are increasingly vulnerable to attacks of all sorts. The stakes for securing data have been rising steadily as the value of that data increases, making it far more attractive to hackers. This is evident in the scope of the attack targets —... » read more

NoCs In 3D Space


A network on chip (NoC) has become an essential piece of technology that enables the complexity of chips to keep growing, but when designs go 3D, or when third-party chiplets become pervasive, it's not clear how NoCs will evolve or what the impact will be on chiplet architectures. A NoC enables data to move between heterogeneous computing elements, while at the same time minimizing the resou... » read more

Paradigms Of Large Language Model Applications In Functional Verification


This paper presents a comprehensive literature review for applying large language models (LLM) in multiple aspects of functional verification. Despite the promising advancements offered by this new technology, it is essential to be aware of the inherent limitations of LLMs, especially hallucination that may lead to incorrect predictions. To ensure the quality of LLM outputs, four safeguarding p... » read more

Blog Review: Apr. 3


Siemens' Keith Felton finds that high bandwidth memory integration poses significant challenges for package designers stemming from its unique architecture and stringent performance requirements. Synopsys' Gervais Fong finds out what's new in the USB4 v2 specification, some of its unique challenges involved in doubling the performance capabilities of the USB wired connection, and an intrigui... » read more

What’s Missing In 2.5D EDA Tools


Gaps in EDA tool chains for 2.5D designs are limiting the adoption of this advanced packaging approach, which so far has been largely confined to high-performance computing. But as the rest of the chip industry begins migrating toward advanced packaging and chiplets, the EDA industry is starting to change direction. There are learning periods with all new technologies, and 2.5D advanced pack... » read more

A New Strategy For Successful Block/Chip Design-Stage Verification


Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening time-to-market constraints and the finite resources at their disposal, while ensuring the quality of their designs remains uncompromised. Traditionally, IC design flows have been depicted as a linear ... » read more

Navigating Design Challenges


Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop v... » read more

V2X Security Is Multi-faceted, And Not All There


Experts at the Table: Semiconductor Engineering sat down to discuss Vehicle-To-Everything (V2X) technology and potential security issues, with Shawn Carpenter, program director, 5G and space at Ansys; Lang Lin, principal product manager at Ansys; Daniel Dalpiaz, senior manager product marketing, Americas, green industrial power division at Infineon; David Fritz, vice president of virtual and hy... » read more

Blog Review: Mar. 27


Cadence's Steve Brown suggests that multi-die technologies will be a key part of the path toward a faster, more efficient chip ecosystem that can support the compressed development cycles now emerging in the automotive industry. Synopsys' John Swanson, Madhumita Sanyal, and Priyank Shukla point to the role of simulation in ensuring seamless operation in the Ethernet ecosystem though rigorous... » read more

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