SoC Power Methodology: Are We Lean Enough


It’s interesting how past lessons learned have such relevance in today’s quest for an optimum system-on chip (SoC) power methodology. Lean manufacturing was introduced by the Toyota Motor Corporation in the 1930s. It is now an essential methodology in most manufacturing and industrial settings. As lean methodology evolved, it extended to software development where its principles have led to... » read more

Smart DFT Infrastructure And Automation Are Key To Managing Design Scaling


This paper describes how using a smarter DFT infrastructure and automation can greatly improve the DFT schedule. A structural DFT infrastructure based on plug-and-play principles is used to enable concurrent DFT development and integration. DFT automation is used to connect and manage the DFT infrastructure to dramatically reduce the risks associated with design scaling and complexity. Highe... » read more

Unknowns Driving Up The Cost Of Auto IC Reliability


Automotive chipmakers are considering a variety of options to improve the reliability of ICs used for everything from sensors to artificial intelligence. But collectively they could boost the number of process steps, increase the time spent in manufacturing and packaging, and stir up concerns about the amount of data that needs to be collected, shared, and stored. Accounting for advanced pro... » read more

What Causes Semiconductor Aging?


Semiconductor technology has evolved to the point where no one can assume chips will last forever. If not carefully considered, aging can shorten the life of an IC below the needs for an intended application. Aging is well studied in technology circles, but while others less directly involved may understand at a general level this is a problem, it's not always obvious why. So what exactly ar... » read more

Simplify DFT For Advanced SoCs


The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

Data Security Challenges In Automotive


Automakers are scrambling to prevent security breaches and data hacks in new vehicles while simultaneously adding new and increasingly autonomous features into vehicles that can open the door to new vulnerabilities. These two goals are often at odds. As with security in any complex system, nothing is ever completely secure. But even getting a handle on this multilayered issue is a challenge.... » read more

ML Focus Shifting Toward Software


New machine-learning (ML) architectures continue to garner a huge amount of attention as the race continues to provide the most effective acceleration architectures for the cloud and the edge, but attention is starting to shift from the hardware to the software tools. The big question now is whether a software abstraction eventually will win out over hardware details in determining who the f... » read more

Addressing Library Characterization And Verification Challenges Using ML


At advanced process nodes, Liberty or library (.lib) requirements are more demanding due to design complexities, increased number of corners required for timing signoff, and the need for statistical variation modeling. This results in an increase in size, complexity, and the number of .lib characterizations. Validation and verification of these complex and large .lib files is a challenging task... » read more

Blog Review: Feb. 2


Synopsys' Stelios Diamantidis shares some predictions for AI in 2022, including the three markets that will push new AI chips, the increasing need for trust chains, the entry of non-traditional companies, and the impact of AI in chip design. Siemens EDA's Ray Salemi checks out how Python and SystemVerilog can work together to boost the verification ecosystem by taking advantage of what each ... » read more

A New Dimension Of Complexity For IC Design


Full 3D designs involving logic-on-logic are still in the tire-kicking stage, but gaps in the tooling already are showing up. This is especially evident with static timing analysis (STA), which is used to validate a design’s timing performance by checking all possible paths for timing violations. STA issues began popping up particularly with the introduction of hybrid bonding, a bumpless p... » read more

← Older posts Newer posts →