tag: Siemens EDA

How Do You Qualify Tools For DO-254 Programs?
By Siemens EDA - 02 Nov, 2022 - Comments: 0

This paper describes the terminology and requirements related to tool qualification specific to the safety-critical programs governed by DO-254 compliance. It also provides some practical examples of tool qualification processes and strategies for commonly used tools. Qualifying tools for DO-254 While the use of state-of-the art development tools has led to ever increasing design complexity... » read more

Blog Review: Nov. 2
By Jesse Allen - 02 Nov, 2022 - Comments: 0

Siemens EDA's Harry Foster examines how successful FPGA projects are in terms of verification effectiveness, finding that only 16% of all FPGA projects were able to achieve no non-trivial bug escapes into production, worse than IC/ASIC in terms of first silicon success. Synopsys' Jamie Boote and The Chertoff Group's David London break down best practice guidance and directives U.S. governmen... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam
By Ann Mutschler - 31 Oct, 2022 - Comments: 12

Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 28 Oct, 2022 - Comments: 0

Automotive, mobility Ford Motor Company revealed it lost $827 million in the third quarter because of parts shortages and unexpected supplier costs. Those shortages affected 40,000 to 50,000 vehicles. The company is shutting down its interest in its self-driving car unit Argo.ai, which it shared with Volkswagen since 2019. Ford will instead focus on advanced driver-assist systems (ADAS), which... » read more

Raising IP Integration Up A Level
By Brian Bailey - 27 Oct, 2022 - Comments: 0

An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Considering The Power Of The Cloud For EDA
By Michael White - 27 Oct, 2022 - Comments: 0

By Michael White, Siemens EDA, in technical collaboration with Peeyush Tugnawat, Google Cloud, and Philip Steinke, AMD At DAC 2022, Google Cloud, AMD, and Calibre Design Solutions presented an EDA in the cloud solution that enables companies to access virtually unlimited compute resources when and as needed to optimize their design and verification flows. If your company is considering addin... » read more

Addressing SRAM Verification Challenges
By Siemens EDA - 26 Oct, 2022 - Comments: 0

SureCore Limited is an SRAM IP company based in Sheffield, the United Kingdom, that develops low power memories for current and next generation silicon process technologies. Its award-winning, world-leading, low power SRAM designs are process independent and variability tolerant, making them suitable for a wide range of technology nodes. Two major product families have been announced: PowerM... » read more

Blog Review: Oct. 26
By Jesse Allen - 26 Oct, 2022 - Comments: 0

Synopsys' Teng-Kiat Lee and Sandeep Mehndiratta argue that IC design in the cloud can support an existing on-prem strategy, enable large and small enterprises to manage cost and capacity more effectively, and offer security for valuable semiconductor IP. Siemens EDA's Chris Spear finds that SystemVerilog classes are a good way to encapsulate both variables and the routines that operates on t... » read more

Testing 2.5D And 3D-ICs
By Ed Sperling - 25 Oct, 2022 - Comments: 0

Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the ... » read more

Bespoke Silicon Rattles Chip Design Ecosystem
By Ann Mutschler - 19 Oct, 2022 - Comments: 0

Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments. Bespoke silicon designers today are a rare breed, capable of understanding the unique requirements of a specific domain, as well as a gr... » read more

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