tag: Siemens

Blog Review: June 30
By Jesse Allen - 30 Jun, 2020 - Comments: 0

Cadence's Paul McLellan examines Fully Homomorphic Encryption, which allows for operations to be performed on encrypted data without decrypting it, and why it's now entering the realm of practicality. Mentor's Shivani Joshi explains the basics of using keepouts to prevent the placement of specific or all design items within a specified area and why they can make or break a first pass at crea... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Jun, 2020 - Comments: 0

Siemens will acquire UltraSoC, a provider of embedded analytics and monitoring solutions for applications including cybersecurity and functional safety. Founded in 2006 and based in Cambridge, U.K., the company's technology will be integrated into the Xcelerator portfolio as part of Mentor’s Tessent software product suite where it will form part of a ‘Design for Lifecycle Management’ stra... » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 26 Jun, 2020 - Comments: 0

Security The U.S. Defense Advanced Research Projects Agency (DARPA) selected Synopsys as the main contractor to provide SoC design tools and security IP for its Automatic Implementation of Secure Silicon (AISS) program. The four-year program’s goal to develop a design tool and IP ecosystem to automate adding security into integrated circuits. Synopsys will be working on a research team with ... » read more

And The Survey Says…
By Brian Bailey - 25 Jun, 2020 - Comments: 0

Some of you may have received an email recently that looks something like this. Others may be getting it in a little while. This is an invitation to participate in a survey that is important for the industry, and I encourage you not to ignore it. Let me explain a little. This survey has quite a long history. It all started in 2002 when Collett International conducted the first survey. Ba... » read more

Post Layout Simulation Is Becoming The Bottleneck For Analog Verification
By Greg Curtis - 25 Jun, 2020 - Comments: 0

My, have times changed. I remember when I first started out as a green analog designer right out of college, we would cut rubylith masking film on a large light table representing the different layers of our design to generate the design for manufacturing of the chip. We proactively worked to mitigate cross coupling of noise to our signal nets, but we were rarely concerned about interconnect re... » read more

Over-Design, Under-Design Impacts Verification
By Ann Mutschler - 25 Jun, 2020 - Comments: 0

Designing a complex chip today and getting it out the door on schedule and within budget — while including all of the necessary and anticipated features and standards — is forcing engineering teams to make more tradeoffs than in the past, and those tradeoffs now are occurring throughout the flow. In an ideal system design flow, design teams will have done early, pre-design analysis to se... » read more

2020 CEO Outlook
By Ed Sperling - 25 Jun, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss the semiconductor industry's outlook and what's changing with Simon Segars, CEO of Arm; Joseph Sawicki, executive vice president of IC EDA at Mentor, a Siemens Business; Raik Brinkmann, CEO of OneSpin Solutions; Babak Taheri, CEO of Silvaco; John Kibarian, CEO of PDF Solutions; and Prakash Narain, CEO of Real Intent. The conversation was part of the... » read more

ML Opening New Doors For FPGAs
By Bryon Moyer - 24 Jun, 2020 - Comments: 0

FPGAs have long been used in the early stages of any new digital technology, given their utility for prototyping and rapid evolution. But with machine learning, FPGAs are showing benefits beyond those of more conventional solutions. This opens up a hot new market for FPGAs, which traditionally have been hard to sustain in high-volume production due to pricing, and hard to use for battery-dri... » read more

EDA In The Cloud — Why Now?
By Mentor, a Siemens Business - 24 Jun, 2020 - Comments: 0

What is the value of cloud computing to my company? Learn how the cloud became a viable option for IC verification, and explore the ways your company can best use cloud resources to expand your compute options for both established nodes and leading-edge technologies. To read more, click here. » read more

Blog Review: June 24
By Jesse Allen - 24 Jun, 2020 - Comments: 0

Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

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