tag: simulation

RF Periodic Stability Analysis
By Various Writers - 09 Apr, 2014 - Comments: 0

The PSTB (periodic stability) analysis feature in Cadence Spectre RF Simulation Option performs stability analysis for circuits with periodically time-varying operating points. PSTB is the periodic equivalent of linear stability (STB) analysis in that it calculates the small-signal loop gain, gain margin, and phase margin around a periodic operating point. PSTB is useful in applications such as... » read more

Formal Is Set To Overtake Simulation
By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

Power Grid Simulation
By Marko Chew - 13 Mar, 2014 - Comments: 1

Introduction The underlying solver algorithms used in power grid (PG) simulation today are derivations of circuit simulation algorithms first developed many decades ago. In fact, the 40th anniversary of SPICE (a widely used circuit simulator), was celebrated in 2011. As such, it is understandable that many engineers have a jaundiced view towards claims of improved PG simulation performance. Ne... » read more

Blog Review: March 12
By Ed Sperling - 12 Mar, 2014 - Comments: 0

Arteris’ Kurt Shuler is sounding the alarm bell for the semiconductor industry. He observes that system OEMs are hiring their own chip engineers. Well, that should wake up someone. Danger Will Robinson. Mentor’s Colin Walls points to a festering debate in the embedded software world about priorities and openness to learning new tools and approaches. Embedded software developers are a rat... » read more

Localized, System-Level Protocol Checks and Coverage Closure Using Veloce
By Various Writers - 29 Jan, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics
By David Hsu - 05 Dec, 2013 - Comments: 0

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for verification tasks is crucial to achieving closure on overall goals, and creating the comprehensive set of metrics to track during the verification process enables schedule predictability and confi... » read more

Experts At The Table: SoC Prototyping
By Ann Mutschler - 12 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: Is it possib... » read more

Experts At The Table: SoC Prototyping
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, for the system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: How... » read more

The New Verification Landscape
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

Shifts In Verification
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

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