tag: simulation

Tech Talk: Power Tools
By Ed Sperling - 27 May, 2015 - Comments: 0

At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

Power Management Verification Requires Holistic Approach
By Ann Mutschler - 14 May, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power management [getkc id="10" kc_name="Verification"] issues with Arvind Shanmugavel, senior director, applications engineering at [getentity id="22021" e_name="Ansys-Apache"]; Guillaume Boillet, technical marketing manager at [getentity id="22026" e_name="Atrenta"]; Adam Sherer, verification product management director at [getentity id="22032" e_... » read more

Tech Talk: Faster SPICE
By Ed Sperling - 04 May, 2015 - Comments: 0

ProPlus CTO Bruce McGaughy explains why FastSPICE (fast Simulation Program with Integrated Circuit Emphasis) is running out of steam in the finFET generation and what needs to happen next. [youtube vid=07XzUQxPUr8] » read more

Is Art Acceptable In Verification?
By Brian Bailey - 23 Apr, 2015 - Comments: 0

The industry appears to have accepted that [getkc id="10" kc_name="verification"] involves art as well as science. This is usually based on one of three reasons, namely: the problem is large and complex; there is a lack of understanding and tools that enable it to be automated; and if it could be made a science, all of the jobs would have migrated offshore. Today, designs are built from pre-... » read more

Is SystemC Broken?
By Brian Bailey - 26 Mar, 2015 - Comments: 19

In order to perform architectural exploration, performance analysis and optimization, early validation of software, improved productivity in hardware development and many other tasks, the industry needs a viable [getkc id="104" kc_name="virtual prototype"]. That requires a suitable language in order to express necessary concepts at a high enough level of [getkc id="101" kc_name="abstraction"] s... » read more

Design By Architect Or Committee?
By Brian Bailey - 26 Mar, 2015 - Comments: 5

Everything we do is based on a language. It doesn’t matter if we are talking about design, verification, specification, software or mask data. They all provide a way to communicate intent, and then there are engines that work on the intent to produce something else that is desirable, also based on a language. Over time, the EDA industry has built up a hierarchy of languages from the most deta... » read more

DDR4 Board Design And Signal Integrity Verification Challenges
By Mentor, a Siemens Business - 25 Mar, 2015 - Comments: 0

This paper, originally presented at DesignCon and nominated for a best paper award, includes an investigation of DDR4's Pseudo Open Drain driver and what its use means for power consumption and Vref levels for the receivers. This paper also examines a DDR4 system design example and the need for simulating with IBIS power aware models versus transistor level models for Simultaneous Switching ... » read more

Clock Domain Crossing (CDC): Are We There Yet?
By Ravindra Aneja - 12 Mar, 2015 - Comments: 0

Over the last decade, SoC designs have become significantly reliant on IP reuse to manage the design complexity and meet time-to-market goals. IP-based design and verification methodology is essential but has put an additional verification burden on IP suppliers (internal and external). IP suppliers need to ensure that their IP is exhaustively verified and SoC Integrators need to ensure that al... » read more

Demonstrating The Benefits Of Source-Mask Optimization And Enabling Technologies Through Experiment And Simulations
By Mentor, a Siemens Business - 19 Feb, 2015 - Comments: 0

In recent years the potential of Source-Mask Optimization (SMO) as an enabling technology for 22nm-and-beyond lithography has been explored and documented in the literature. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the mask and the source, which leads to improved lithograp... » read more

Emulation Uses Increase
By Ed Sperling - 12 Feb, 2015 - Comments: 0

For more than two decades, [getkc id="30" comment="emulation"] was a technology in search of a market. While on paper it has always made sense to speed up simulation, using hardware acceleration was so pricey that few companies could justify the cost. Fast-forward to today and emulation is a major contributor to the bottom line at all of the Big Three [getkc id="7" kc_name="EDA"] companies. ... » read more

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