IC Compiler II Multi-Level Physical Hierarchy Floorplanning

By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

Bridging Hardware And Software

By Ann Mutschler - 22 Dec, 2015 - Comments: 0

Since the advent of embedded systems there has been a struggle between hardware engineers trying to understand the mindset of their software counterparts, and vice versa. That struggle is alive and well today—and it's costing everyone money. This divide is rife with passion, territoriality and misunderstanding. It has delayed tapeouts, created errors and inefficiencies that take time and e... » read more

Reflections On 2015

By Brian Bailey - 22 Dec, 2015 - Comments: 0

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with SemiEngineering. We like to hold people's feet to the fire, but while the Pants-On-Fire meter may be applicable to politicians, we like to thin... » read more

Developing Effective Design Strategies for Today’s Wearable Devices: Power Management

By Mentor, a Siemens Business - 21 Dec, 2015 - Comments: 0

As the next wave of wearable devices expands into a new class of revolutionary and innovative products, there will be a growing importance placed on the real-time operating system (RTOS) and corresponding middleware. Wearable System-on-Chip (SoC) processors require an operating system optimized for size and performance with power-efficient wireless connectivity options needed for machine-to-mac... » read more

C-Based SoC Design Flow And EDA Tools

By Aldec - 21 Dec, 2015 - Comments: 0

This paper examines the achievements and future of SoC design methodology and design flow from the viewpoints of an in- house EDA team of an ASIC and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC’s complexity and the timing closure caused by deep submicron technology. To solve these two problems, we propose a C-based SoC design environment t... » read more

Rethinking Memory

By Ed Sperling - 16 Dec, 2015 - Comments: 3

Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

What Goes Wrong With IP

By Ed Sperling - 10 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

Defining Sufficient Coverage

By Brian Bailey - 07 Dec, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

The Challenge Of Fitting In

By Ann Mutschler - 30 Nov, 2015 - Comments: 0

Connections between players in the semiconductor industry are becoming critical for survival. Whether the focus is a connected car, home automation, health care or the energy grid, each company in each of those markets relies on others to build useful products. There are several forces at work here. One is an emphasis on connecting everything, regardless of whether it is inside a single vert... » read more

Do Circuits Whisper Or Shout?

By Ann Mutschler - 18 Nov, 2015 - Comments: 0

Maximizing SoC performance and minimizing power is becoming a multi-layered and multi-company challenge that depends on everything from ecosystem feedback and interactions to micro-architectural decisions about whether analog circuits whisper or shout. What used to be a straightforward architectural tradeoff between performance and power has evolved into a much more diffuse and collaborativ... » read more

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Knowledge Centers
Entities, people and technologies explored

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A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

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NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: SoC