Large-Scale Integration’s Future Depends On Modeling

By Karen Heyman - 27 Jul, 2023 - Comments: 0

VLSI is a term that conjures up images of a college textbook, but some of the concepts included in very large-scale integration remain relevant and continue to evolve, while others have fallen by the wayside. The portion of VLSI that remains most relevant for semiconductor industry is "integration," which is pushing well beyond the edges of a monolithic planar chip. But that expansion also i... » read more

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)

By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "ObNoCs: Protecting Network-on-Chip Fabrics Against Reverse-Engineering Attacks" was published by researchers at University of Florida. Abstract: "Modern System-on-Chip designs typically use Network-on-Chip (NoC) fabrics to implement coordination among integrated hardware blocks. An important class of security vulnerabilities involves a rogue foundry reverse-engineeri... » read more

The Design Automation Conference Turns 60! What’s Hot? What’s Next?

By Frank Schirrmeister - 06 Jul, 2023 - Comments: 0

This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco to discuss aspects of what we call "Electronic Design Automation" (EDA) and typically associate with hardware development. There will be many celebratory elements this year, given the milestone of 60 years. Industry luminary Alberto Sangiovanni Vincentelli will give o... » read more

Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)

By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip” was published by researchers at University of Montpellier and University of Vale do Itajaí. Abstract: "Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables... » read more

An Automated Method For Adding Resiliency To Mission-Critical SoC Designs

By Synopsys - 21 Jun, 2023 - Comments: 0

Adding safety measures to system-on-chip (SoC) designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the Aerospace and Defense (A&D), cloud, automotive, robotics, medical, and Internet-of-Things (IoT) industries more resilient against random hardware failures that occur. Designing for reliable and resilient functionality doe... » read more

Advanced RISC-V Verification Methodology Projects

By Imperas - 24 May, 2023 - Comments: 0

The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse, and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this a... » read more

Pinpointing Timing Delays Can Improve Chip Reliability

By Anne Meixner - 09 May, 2023 - Comments: 0

Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

Design Considerations and Recent Advancements in Chiplets (UC Berkeley/ Peking University)

By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "Automated Design of Chiplets" was published by researchers at UC Berkeley and Peking University. Abstract: "Chiplet-based designs have gained recognition as a promising alternative to monolithic SoCs due to their lower manufacturing costs, improved re-usability, and optimized technology specialization. Despite progress made in various related domains, the des... » read more

How Low Can You Go? Pushing The Limits Of Transistors

By Synopsys - 08 Mar, 2023 - Comments: 0

Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

Design IP

By Cadence - 01 Mar, 2023 - Comments: 0

Cadence is a leader in semiconductor IP addressing hyperscale computing, enterprise, data center, automotive, and artificial intelligence/machine learning (AI/ML) applications. Our IP are available in advanced-process nodes ranging from 28nm to 3nm—all silicon verified in leading-edge foundry processes. Our memory IP portfolio spans DDR, LPDDR, and GDDR. The Cadence® IP family for PCI Expres... » read more

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tag: SoC

Large-Scale Integration’s Future Depends On Modeling

NoC Obfuscation For Protecting Against Reverse Engineering Attacks (U. Of Florida)

The Design Automation Conference Turns 60! What’s Hot? What’s Next?

Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)

An Automated Method For Adding Resiliency To Mission-Critical SoC Designs

Advanced RISC-V Verification Methodology Projects

Pinpointing Timing Delays Can Improve Chip Reliability

Design Considerations and Recent Advancements in Chiplets (UC Berkeley/ Peking University)

How Low Can You Go? Pushing The Limits Of Transistors

Design IP

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