tag: SoC

Going Beyond The Requirements Of A Root Of Trust For Measurement With The Silicon-Proven RT-660 Root of Trust
By Rambus - 30 Nov, 2022 - Comments: 0

The continuously evolving technology landscape and security requirements for systems present many challenges for device and silicon manufacturers. Nowhere is this truer than in data centers. Rambus has long recognized the need for security designs in data centers, and the Caliptra initiative discussed in this whitepaper is a welcome step towards a widespread adoption of Root of Trust designs i... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm
By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

Faster And Smarter LVS For The SoC Era
By Synopsys - 26 Oct, 2022 - Comments: 0

Development of a modern system-on-chip (SoC) device is a long and incredibly complex process. Design teams rely on a huge range of tools, technologies, and methodologies to get the job done. Given the ongoing advances in silicon technology and design architecture, the tools are in a constant state of evolution. Logic-versus-schematic (LVS) checking is one of those tools. This is one of the earl... » read more

Efficient Verification Of Mixed-Signal Series IP Using UVM
By Cadence - 21 Sep, 2022 - Comments: 0

Interface IP are an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal ... » read more

Faster & Smarter LVS For The SoC Era
By Synopsys - 21 Sep, 2022 - Comments: 0

Development of a modern system-on-chip (SoC) device is a long and incredibly complex process. Design teams rely on a huge range of tools, technologies, and methodologies to get the job done. Given the ongoing advances in silicon technology and design architecture, the tools are in a constant state of evolution. Logic-versus-schematic (LVS) checking is one of those tools. This is one of the earl... » read more

Designing for FPGA Accelerators
By Technical Paper Link - 31 Aug, 2022 - Comments: 0

This research paper titled "High-Level Synthesis Hardware Design for FPGA-based Accelerators: Models, Methodologies, and Frameworks" was published by researchers at Università degli Studi di Trieste (Italy), Universidad Nacional de San Luis (Argentina), and the Abdus Salam International Centre for Theoretical Physics (Italy). According to the paper's abstract, "This paper presents a survey ... » read more

Traceability Is Not My Problem (Is It?)
By Paul Graykowski - 21 Jun, 2022 - Comments: 0

What is all the fuss about traceability? If it is that important, should it be handled by a compliance group? Delegating to a separate team would be the preference for most design and verification team members, but it is not possible in this case. Traceability stops short of a big brother organization constantly looking over the shoulders of the development team. The more reasonable approach is... » read more

Where And When End-to-End Analytics Works
By Anne Meixner - 10 May, 2022 - Comments: 0

With data exploding across all manufacturing steps, the promise of leveraging it from fab to field is beginning to pay off. Engineers are beginning to connect device data across manufacturing and test steps, making it possible to more easily achieve yield and quality goals at lower cost. The key is knowing which process knob will increase yield, which failures can be detected earlier, and wh... » read more

A Holistic Approach To Energy-Efficient System-On-Chip (SoC) Design
By Synopsys - 10 May, 2022 - Comments: 0

It takes a great deal of energy to power the modern world, and demand grows every day. This is especially true for electronics, where ever increasing automation and more intelligent devices incessantly demand more power. Many applications that use chips face a variety of pressures for reduced power consumption and better energy efficiency. In response, the semiconductor and electronic design au... » read more

Software-Driven and System-Level Tests Drive Chip Quality
By Bryon Moyer - 08 Mar, 2022 - Comments: 0

Traditional semiconductor testing typically involves tests executed by automatic test equipment (ATE). But engineers are beginning to favor an additional late-test pass that tests systems-on-chip (SoCs) in a system context in order to catch design issues prior to end-product assembly. “System-level test (SLT) gives a high-volume environment where you can test the hardware and software toge... » read more

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