The Week In Review: July 22

By Mark LaPedus - 22 Jul, 2013 - Comments: 0

By Mark LaPedus ASML Holding has been under pressure to bring extreme ultraviolet (EUV) lithography into mass production. EUV is still delayed. Now, in their latest roadmaps, leading-edge chipmakers are counting on ASML’s 300mm EUV scanner for insertion at the 10nm node. Yet, at the same time, ASML also is working on a 450mm version of the EUV tool. “EUV (on 300mm) is a higher priority th... » read more

450mm: Out Of Sync

By Mark LaPedus - 18 Jul, 2013 - Comments: 0

By Mark LaPedus The IC industry has been talking about it for ages, but vendors are finally coming to terms with a monumental shift in the business. The vast changes involve a pending and critical juncture, where the 450mm wafer size transition, new device architectures and other technologies will likely converge at or near the same time. In one possible scenario, 450mm fabs are projected ... » read more

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP

By Various Writers - 17 Jul, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~ ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30% increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

The Week In Review: July 15

By Mark LaPedus - 15 Jul, 2013 - Comments: 0

By Mark LaPedus There are more problems surfacing with extreme ultraviolet (EUV) lithography. Yes, the light source remains a problem, but the resists appear to be in decent shape. “The next challenge is the mask blank,” said Stefan Wurm, director of Sematech’s lithography program. The new problem involves ion beam deposition, which apparently is causing defects and overfill on EUV masks... » read more

The Shape Of Things To Come

By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The standard method of designing chips—by shrinking features and turning up the clock frequency—is running out of steam for many companies. It’s too difficult, too expensive, and without a commercially viable new lithography source it may become even more unrealistic for most applications. That certainly doesn’t mean Moore’s Law is ending, but it could become more o... » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design

By Ed Sperling - 04 Jun, 2013 - Comments: 0

Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

New Foundry Gold Rush: RF SOI

By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus About every five years or so, a new and hot market emerges in the specialty foundry business that resembles a frenetic gold rush. The last big gold rush occurred around 2008, when more than a dozen foundries jumped into the bipolar-CMOS-DMOS (BCD) market to capitalize on the booming power-management sector. Now, the next gold rush is centering on an emerging technology—th... » read more

Moving Targets

By Ed Sperling - 16 May, 2013 - Comments: 0

There is a very close correlation between power and complexity in an SoC. The more functionality that is required to meet market demands, the greater the need to push to the next process node in order to fit it all onto a single die. The result is more power density, and more attempts to limit the effects of that density with power islands, different voltages, gating, and a variety of other tec... » read more

FinFET Isolation: Bulk vs. SOI

By Various Writers - 15 May, 2013 - Comments: 1

Terry Hook of IBM recently contributed an article to ASN about FinFET isolation issues on bulk vs. SOI. It generated immense interest, and created lots of discussion on various LinkedIn groups. In case you missed it, here it is again. (This article is based on an in-depth presentation Terry gave at the SOI Consortium's Fully-Depleted Tech Workshop, held during VLSI-TSA in Taiwan, April 2... » read more

FinFETs On SOI

By Ed Sperling - 13 May, 2013 - Comments: 0

Soitec's Steve Longoria talks with Semiconductor Manufacturing and Design about what's changing at the leading edge of Moore's Law and why those changes are necessary. [youtube vid=K6D39QqJWSU] » read more

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