Faster Assembly Required

By Ed Sperling - 27 Jun, 2013 - Comments: 0

Speeding up production has been a mantra dating back throughout recorded history, and presumably well before that. That’s what technology was created for—roads, bridges aqueducts, computers, the Internet, and everything that connects the real to the virtual world. A speech by Nvidia chief scientist Bill Dally at DAC that complex SoCs should only take a couple weeks to design by two guys ... » read more

3D-IC Testing With The Mentor Graphics Tessent Platform

By Various Writers - 20 Jun, 2013 - Comments: 0

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time. 3D chips connected via interposers are in production at Xilinx, Samsung, IBM, and Sematec... » read more

Marching Orders

By Ed Sperling - 20 Jun, 2013 - Comments: 0

Reports back from the front lines of Moore’s Law are rather consistent—14nm and 16nm finFETs are do-able, but they’re not easy to design, verify or manufacture. In fact, the only high-volume source of production-proven finFETs at this point is Intel, which is turning them out at 22nm. A number of issues are cropping up at the most advanced nodes, and while each is ultimately solvable, ... » read more

The Shape Of Things To Come

By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The standard method of designing chips—by shrinking features and turning up the clock frequency—is running out of steam for many companies. It’s too difficult, too expensive, and without a commercially viable new lithography source it may become even more unrealistic for most applications. That certainly doesn’t mean Moore’s Law is ending, but it could become more o... » read more

Pushing The Limits

By Ed Sperling - 13 Jun, 2013 - Comments: 0

Ever since the turn of the millennium, researchers have been warning that wires and interconnects will have issues. Electron crashes were reported as early as 2001, and electromigration is rising to the forefront of problems at advanced nodes. The result? Chipmakers are looking at thicker wires for the first time as a way of dealing with resistance and capacitance issues. While this makes se... » read more

Experts At The Table: The Growing Signoff Headache

By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Tech Talk: FinFETs, FD-SOI And The Future Of SoC Design

By Ed Sperling - 04 Jun, 2013 - Comments: 0

Mary Ann White, marketing manager for Synopsys' Galaxy Implementation Platform, talks with Low-Power/High-Performance Engineering about new opportunities to reduce power and improve performance, and where the pain points will be. [youtube vid=kuJdcHIRxfU] » read more

Executive Briefing: Stacking The Odds

By Ed Sperling - 29 May, 2013 - Comments: 0

Open-Silicon CEO Naveed Sherwani talks with System-Level Design about progress on 2.5D and 3D stacked die, why this approach is inevitable, when it will begin and what markets will use it first. [youtube vid=mzwpgDKuIok] » read more

3D Brings Test Into Fashion

By Ann Mutschler - 16 May, 2013 - Comments: 0

By Ann Steffora Mutschler As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable. But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to... » read more

3D NAND Market Heats Up

By Mark LaPedus - 16 May, 2013 - Comments: 0

By Mark LaPedus It’s the tale of two promising and separate 3D chip architectures. One technology is slowly taking root, while the other one is heating up. 3D stacked-die using through-silicon vias (TSVs) is on the slower path. Advanced chip-stacking has several challenges and is still a few years away from mass production. In contrast, 3D NAND is heating up, as Samsung and SK Hynix are a... » read more

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Knowledge Centers
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