tag: STATS ChipPAC

Advanced Packaging’s Progress
By Mark LaPedus - 09 Oct, 2017 - Comments: 0

Shim Il Kwon, CTO at STATS ChipPAC, sat down with Semiconductor Engineering to discuss the current and future trends of chip packaging. What follows are excerpts of that conversation. SE: The outsourced semiconductor assembly and test (OSAT) vendors provide third-party IC-packaging and test services. What are the big challenges for OSATs today? Shim: The OSAT market is very competitive, w... » read more

Advanced Packaging For Automotive Dashboard Application
By STATS ChipPAC - 11 Sep, 2017 - Comments: 0

The current automotive market for the IC (integrated circuit) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting it... » read more

Get Ready For In-Mold Electronics
By Jeff Dorsch - 11 Sep, 2017 - Comments: 1

Imagine inserting the electronics into a product without using a printed circuit board, a module, or even a system-in-package. That's the promise of in-mold electronics (IME), a technology that has been around for years, but which is just beginning to see wider adoption. The technology is related to conductive inks and transparent conductive films. The IME manufacturing process is said to pr... » read more

Cheaper Fan-Outs Ahead
By Mark LaPedus - 07 Aug, 2017 - Comments: 6

Packaging houses continue to ramp up fan-out wafer-level packages in the market, but customers want lower cost fan-out products for a broader range of applications, such as consumer, RF and smartphones. So in R&D, the industry for some time has been developing next-generation fan-out using a panel-level format, a technology that could potentially lower the cost of fan-out. But there are ... » read more

Fine-Pitch Copper Pillar With Bond On Lead (BOL).
By STATS ChipPAC - 07 Aug, 2017 - Comments: 0

Fine pitch copper (Cu) pillar bump adoption has been growing in high-performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities. Assembling such packages u... » read more

Advanced Packaging Moves To Cars
By Ann Mutschler - 07 Aug, 2017 - Comments: 0

By Ann Steffora Mutschler and Ed Sperling As automotive OEMs come up to speed on electrification of vehicles, each at their own pace, they are starting to embrace novel packaging approaches as a way to differentiate themselves in an increasingly competitive market. Wirebond used to dominate this market, where most of the chips were relatively unsophisticated and product cycles were slow�... » read more

28nm Chip-Package Interactions In Large eWLB FO-WLP
By STATS ChipPAC - 10 Jul, 2017 - Comments: 0

To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabl... » read more

Advanced Packaging Picks Up Steam
By Jeff Dorsch - 10 Jul, 2017 - Comments: 0

The semiconductor industry’s push toward continued miniaturization and increasing complexity is driving wider adoption of system-in-package (SiP) technology. One of the big benefits of [getkc id="199" kc_name="SiP"] is that it allows more features to be squeezed into ever-smaller form factors, such as wearable gadgets and medical implants. So while the individual chips in this package may ... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

Shrink Or Package?
By Ed Sperling - 19 Jun, 2017 - Comments: 0

Advanced packaging is rapidly becoming a mainstream option for chipmakers as the cost of integrating heterogeneous components on a single die continues to rise. Despite several years of buzz around this shift, the reality is that it has taken more than a half-century to materialize. Advanced [getkc id="27" kc_name="packaging"] began with IBM flip chips in the 1960s, and it got another boost ... » read more

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