tag: STI

Improving The Gate Oxide Reliability in Gate First HKMG DRAM Structures (Sungkyunkwan Univ., Samsung)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Novel STI Technology for Enhancing Reliability of High-k/Metal Gate DRAM" was published by researchers at Sungkyunkwan University and Samsung Electronics. Abstract: "The challenges associated with semiconductor are increasing because of the rapid changes in the semiconductor market and the extreme scaling of semiconductors, with some processes reaching their te... » read more

Managing Yield With EUV Lithography And Stochastics
By Katherine Derbyshire - 18 May, 2023 - Comments: 1

Identifying issues that actually affect yield is becoming more critical and more difficult at advanced nodes, but there is progress. Although they are closely related, yield management and process control are not the same. Yield management seeks to maximize the number of functioning devices at the end of the line. Process control focuses on keeping each individual device layer within its des... » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance
By Coventor - 15 Sep, 2021 - Comments: 1

In this paper, a 5nm FinFET flow was built using the SEMulator3D virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated usi... » read more

Ion Implanter Market Heats Up
By Mark LaPedus - 14 Aug, 2014 - Comments: 0

The ion implanter market has been a stable, if not a sleepy, business. The last big event took place in 2011, when Applied Materials re-entered the ion implanter market by acquiring Varian, the world’s leading supplier of these tools. The acquisition gave Applied Materials a commanding 80% share of the implanter business, with the other players fighting for the crumbs. But after year... » read more

Overcoming Shallow Trench Isolation
By Kathryn Ta - 20 Jun, 2013 - Comments: 0

By Kathryn Ta To prevent electrical current leaking between adjacent transistors, state-of-the-art microchips feature shallow trench isolation (STI) to isolate transistors from each other. Key steps in the STI process involve etching a pattern of trenches in the silicon, depositing dielectric materials to fill the trenches, and removing the excess dielectric using technologies such as chemical... » read more

Fabless-Foundry Model Under Stress
By Ed Sperling - 26 Jun, 2012 - Comments: 0

By Mark LaPedus The semiconductor roadmap was once a smooth and straightforward path, but chipmakers face a bumpy and challenging ride as they migrate to the 20nm node and beyond. Among the challenges seen on the horizon are the advent of 3D stacking, 450mm fabs, new transistor architectures, multi-patterning, and the questionable availability of extreme ultraviolet (EUV) lithography. ... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy