tag: SUNY Polytechnic Institute

Chip Industry’s Technical Paper Roundup: July 18
By Liz Allan - 18 Jul, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=118 /] (more…) » read more

TaN Nanowires At 300 mm Wafer Scale For Quantum Computing And More
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "Ultra-thin TaN Damascene Nanowire Structures on 300 mm Si Wafers for Quantum Applications" was published by researchers at NY CREATES, United States Air Force Research Laboratory and SUNY Polytechnic Institute. Abstract: "We report on the development and characterization of superconducting damascene tantalum nitride (TaN) nanowires, 100 nm to 3 μm wide, with TaN thi... » read more

New Challenges Emerge With High-NA EUV
By Katherine Derbyshire - 16 Mar, 2023 - Comments: 3

High numerical aperture EUV exposure systems are coming — as soon as 2025 by some estimates. Though certainly a less profound change than the introduction of extreme ultraviolet lithography, high-NA lithography still brings a new set of challenges for photoresists and related materials. With a higher numerical aperture, photons strike the wafer at a shallower angle. That requires thinner p... » read more

Driving Toward More Rugged, Less Expensive SiC
By Katherine Derbyshire - 19 May, 2022 - Comments: 0

Silicon carbide is gaining traction in the power semiconductor market, particularly in electrified vehicles, but it's still too expensive for many applications. The reasons are well understood, but until recently SiC was largely a niche technology that didn't warrant the investment. Now, as demand grows for chips that can work in high-voltage applications, SiC is getting a much closer look. ... » read more

How AI/ML Improves Fab Operations
By Laura Peters - 10 May, 2022 - Comments: 0

Chip shortages are forcing fabs and OSATs to maximize capacity and assess how much benefit AI and machine learning can provide. This is particularly important in light of the growth projections by market analysts. The chip manufacturing industry is expected to double in size over the next five years, and collective improvements in factories, AI databases, and tools will be essential for doub... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 02 Jul, 2020 - Comments: 0

Fab tools, packaging/test VLSI Research has released its 200mm wafer fab equipment (WFE) market share figures for 2019. The top three suppliers--Applied Materials, TEL, and ASML—saw growth in the 2019 200mm WFE business. Lam Research was in fourth place, followed by KLA and Canon. In total, 200mm wafer fab equipment sales were $3.6 billion in 2019, declining 5% from 2018, according to the fi... » read more

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Sep, 2019 - Comments: 0

Chipmakers United Microelectronics Corp. (UMC) has satisfied all closing conditions for the full acquisition of Mie Fujitsu Semiconductor Ltd. (MIFS), the former 300mm wafer foundry joint venture between UMC and Fujitsu Semiconductor Ltd. (FSL). The completion of the acquisition is scheduled for Oct. 1. In 2014, FSL and UMC agreed for UMC to acquire a 15.9% stake in MIFS from FSL through pr... » read more

Integrated Photonics (Part 3)
By Brian Bailey - 12 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the status of integrated photonics with Twan Korthorst, CEO for PhoeniX Software; Gilles Lamant, distinguished engineer for [getentity id="22032" e_name="Cadence"]; Bill De Vries, director of marketing for Lumerical Solutions; and Brett Attaway, director of EPDA solutions at AIM Photonics, SUNY Polytechnic Institute. What follows are excerpts of tha... » read more

System Bits: June 6
By Ann Mutschler - 06 Jun, 2017 - Comments: 0

Silicon nanosheet-based builds 5nm transistor To enable the manufacturing of 5nm chips, IBM, GLOBALFOUNDRIES, Samsung, and equipment suppliers have developed what they say is an industry-first process to build 5nm silicon nanosheet transistors. This development comes less than two years since developing a 7nm test node chip with 20 billion transistors. Now, they’ve paved the way for 30 billi... » read more

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