Who Does Processor Validation?


Defining what a processor is, and what it is supposed to do, is not always as easy as it sounds. In fact, companies are struggling with the implications of hundreds of heterogenous processing elements crammed into a single chip or package. Companies have extensive verification methodologies, but not for validation. Verification is a process of ensuring that an implementation matches a specif... » read more

Week In Review: Design, Low Power


RISC-V RISC-V International announced four new specification and extension approvals. Efficient Trace for RISC-V defines an approach to processor tracing that uses a branch trace. RISC-V Supervisor Binary Interface architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode to enable common platform services... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility The U.S. Department of Transportation’s National Highway Traffic Safety Administration (NHTSA) published a notice of proposed rulemaking (NPRM) to change the regulations on event data recorders (EDRs) to extend the EDR recording period for “timed data metrics from 5 seconds of pre-crash data at a frequency of 2 Hz to 20 seconds of pre-crash data at a frequency of 10 Hz... » read more

EDA Embraces Big Data Amid Talent Crunch


The semiconductor industry’s labor crunch finally has convinced chip designers to bet big money on big data. As recently as 2016, executives weren’t sure there was a market for big data approaches to electronic design automation. The following year, utilization of big data remained stuck in its infancy. And in 2018, Semiconductor Engineering questioned why the EDA sector wasn’t investi... » read more

Blog Review: June 22


Arm's Andrew Pickard checks out a project at Sorbonne Université in Paris that is using the Cortex-M3 processor source code to model what is happening in the hardware at the microarchitectural level and find ways to prevent side-channel leakage of sensitive cryptographic information. Cadence's Paul McLellan digs into the development of high-NA EUV lithography and some of the challenges ahea... » read more

Power Domain Implementation Challenges Escalate


The number power domains is rising as chip architects build finer-grained control into chips and systems, adding significantly to the complexity of the overall design effort. Different power domains are an essential ingredient in partitioning of different functions. This approach allows different chips in a package, and different blocks in an SoC, to continue running with just enough power t... » read more

Week In Review: Manufacturing, Test


Node scaling wars are revving up, although much of the action is happening where most people can't see it — inside of research labs. This is difficult stuff, which makes delivery dates difficult to pinpoint, and no one wants to give away their competitive position or commit to a timeline they can't keep. Billions of dollars of leading-edge research — funded by pure-play foundry TSMC, IDM... » read more

Week In Review: Design, Low Power


Tools, design, chips Altair, a provider of software and cloud services for CAE, HPC, simulation, and data analysis, acquired Concept Engineering, a provider of automatic schematic generation tools, electronic circuit and wire harness visualization platforms that provide on-the-fly visual rendering, and electronic design debug solutions. “Concept Engineering’s advanced, reactive visualizati... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility U.S. National Highway Traffic Safety Administration (NHTSA) release its first crash reports from ADAS (advanced driver assistance systems, i.e., SAE Level 2) and ADS (automated driving systems, i.e., SAE Levels 3-5).  The systems had to be in use at least 30 seconds before the crash in order for it to be reportable. The car may have had the system turned off at the time ... » read more

Variation Making Trouble In Advanced Packages


Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

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