Designing ASIPs With Confidence


Well-designed ASIPs with a strong SDK combine C/C++ programmability with the power and performance of dedicated hardware. Product families based on ASIP platforms are often highly flexible, capable of addressing multiple market segments with the same silicon and handling updates in the field. They lean well towards software-driven verification with few penalties for late product requirement cha... » read more

Blog Review: March 10


Siemens EDA's Harry Foster checks out how the maturity of verification processes impact bug escapes in FPGA designs and whether safety critical development processes prevent bugs from escaping to silicon. Synopsys' Dennis Kengo Oka examines the weaknesses and vulnerabilities in automotive keyless entry systems and how security researchers hacked the Tesla Model X key fob. Cadence's Paul M... » read more

Preventing Chips From Burning Up During Test


It’s become increasingly difficult to manage the heat generated during IC test. Absent the proper mitigations, it’s easy to generate so much heat that probe cards and chips literally can burn up. As a result, implementing temperature-management techniques is becoming a critical part of IC testing. “We talk about systems, saying the system is good,” said Arun Krishnamoorthy, senior... » read more

Cloud Vs. On-Premise Analytics


The immense and growing volume of data generated in chip manufacturing is forcing chipmakers to rethink where to process and store that data. For fabs and OSATs, this decision is not one to be taken lightly. The proprietary nature of yield, performance, and other data, and corporate policies to retain tight control of that data, have so far limited outsourcing to the cloud. But as the amount... » read more

Making Sure AI/ML Works In Test Systems


Artificial intelligence/machine learning is being utilized increasingly to find patterns and outlier data in chip manufacturing and test, improving the overall yield and reliability of end devices. But there are too many variables and unknowns to reliably predict how a chip will behave in the field using just AI. Today, every AI use case — whether a self-driving car or an industrial sortin... » read more

Finally, Analyzing All Test And Manufacturing Data Automatically


Product quality and yield, operational efficiency, and time-to-market continue to be dominant drivers in the semiconductor industry. Adding to this complexity is a diverse manufacturing and test supply-chain of independent providers all continuously generating enormous amounts of different types of chip-related data in various formats. The knowledge contained within this data is critical to pro... » read more

Week In Review: Design, Low Power


Tools Synopsys introduced Euclide, a next-generation hardware description language (HDL)-aware integrated development environment (IDE). Euclide aims to enable earlier detection of bugs and optimize code for design and verification flows by identifying complex design and testbench compliance checks during SystemVerilog and UVM development. It assists correct-by-construction code development th... » read more

Auto OEMs Face New Competitive Threats


Automotive design and manufacturing are undergoing a fundamental shift to the left as cars increasingly are electrified and chips take over more functions formerly done by mechanical parts, setting the stage for massive disruption across a supply chain that has been in place for decades. The success of Tesla — a company that had never actually built a chip or a car — was both a surprise ... » read more

Making Vehicle Electronics Safe With ISO 26262 Compliance


There are many semiconductor applications with high demands on safety, including spaceborne systems, nuclear power plants, and embedded medical devices. But automotive electronics are probably foremost in most peoples’ minds when they think about safe operation under all conditions. The advent of fully autonomous vehicles is responsible for much of this attention. Like other safety-critical a... » read more

Blog Review: March 3


Siemens EDA's Ray Salemi considers incrementalism in engineering, the transition from drawing circuits to writing RTL, and the next big leap of using proxy-driven testbenches written in Python. Cadence's Shyam Sharma looks at key changes from LPDDR5 in the LPDDR5X SDRAM standard, which extends clock frequencies to include 937MHz and 1066MHz resulting in max data rates of 7500MT/s and 8533 MT... » read more

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