tag: Synopsys

Blog Review: June 24
By Jesse Allen - 24 Jun, 2020 - Comments: 0

Cadence's Paul McLellan provides an overview of the new IEEE 1838 standard for manufacturing test of 3D stacked ICs and how it aims to enable testing of multi-die chiplet-based designs. In a video, Mentor's Colin Walls investigates the scope and lifetime of pointers in embedded applications. A Synopsys writer checks out the latest mobile memory standard, JESD209-5A, and the enhancements i... » read more

Eliminate Silicon Respins With Netlist CDC Verification
By Synopsys - 24 Jun, 2020 - Comments: 0

Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for advanced designs and complex flows, there is significant logic optimization during RTL synthesis as well as backend flows at the netlist stage. This mandates clock domain crossing verification a must for... » read more

What’s After PAM-4?
By Bryon Moyer - 23 Jun, 2020 - Comments: 1

[This is part 2 of a 2-part series. Part 1 can be found here.] The future of high-speed physical signaling is uncertain. While PAM-4 remains one of the key standards today, there is widespread debate about whether PAM-8 will succeed it. This has an impact on everything from where the next bottlenecks are likely to emerge and the best approaches to solving them, to how chips, systems and p... » read more

Week In Review: Design, Low Power
By Jesse Allen - 19 Jun, 2020 - Comments: 0

Tools & IP Rambus debuted 112G XSR/USR PHY IP on TSMC's N7 7nm process. The PHY IP enables die-to-die and die-to-optical engine connectivity for chiplets and co-packaged optics targeting data center, networking, 5G, HPC, and AI/ML applications. It has been demonstrated in silicon to exceed the reach/BER performance of the CEI-112G XSR specification and supports NRZ and PAM-4 signaling at v... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 19 Jun, 2020 - Comments: 0

Security Many IoT devices have some of the 19 bugs known as Ripple20 vulnerabilities. Researchers JSOF discovered the security flaws in library produces by Treck, Inc., which is used in many IoT devices. Edge, cloud, data center Rambus delivered its 112G XSR/USR PHY IP on TSMC 7nm process (N7). The SerDes PHY was designed for chiplets and co-packaged optics (CPO) architectures that are des... » read more

High-Speed Signaling Drill-Down
By Bryon Moyer - 17 Jun, 2020 - Comments: 0

Chip interconnect standards have received a lot of attention lately, with parallel versions proliferating for chiplets and serial versions moving to higher speeds. The lowliest characteristic of these interconnect schemes is the physical signaling format. Having been static at NRZ (non-return-to-zero) for decades, change is underway. “Multiple approaches are likely to emerge,” said Brig ... » read more

Blog Review: June 17
By Jesse Allen - 17 Jun, 2020 - Comments: 0

Mentor's Chris Spear provides an introduction to SystemVerilog Multidimensional Arrays and shares code samples to follow along. Cadence's Paul McLellan listens in on Sophie Wilson's 2020 Wheeler Lecture that traces the history of the microprocessor from the early days of Moore's Law through to increasing power and economic constraints that are causing a transition from general purpose to spe... » read more

Interconnect Challenges Grow, Tools Lag
By Brian Bailey - 15 Jun, 2020 - Comments: 2

Interconnects are becoming much more problematic as devices shrink and the amount of data being moved around a system continues to rise. This limitation has shown up several times in the past, and it's happening again today. But when the interconnect becomes an issue, it cannot be solved in the same way issues are solved for other aspects of a chip. Typically it results in disruption in how ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Jun, 2020 - Comments: 0

Synopsys acquired Qualtera, a provider of big data analytics for semiconductor test and manufacturing. Based in Montpellier, France and founded in 2010, Qualtera's Silicondash platform provides both off-line and in-line modules for data analytics, visualization, simulation, and modeling to allow for development of control strategies. Combined with Synopsys' TestMAX test automation solution, the... » read more

Week In Review: Auto, Security, Pervasive Computing
By SE Staff - 12 Jun, 2020 - Comments: 0

Edge, cloud, data center Programmable logic company Efinix used Cadence’s Digital Full Flow to finish Efinix’s Trion FPGA family for edge computing, AI/ML and vision processing applications, according to a press release. Last week Efinix also announced three software defined SoCs based on the RISC-V core. The SoCs are optimized to the Trion FPGAs. AI, machine learning Amazon will tempo... » read more

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