tag: Synopsys

Stacked Die Moves From Drawing Board To Reality
By Ed Sperling - 21 Nov, 2013 - Comments: 0

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbo... » read more

Verifying Cache Coherency Protocols With Verification IP
By Various Writers - 21 Nov, 2013 - Comments: 0

The use of on-chip cache memory helps design teams optimize multicore designs for both power and performance. While the use of hardware to implement cache coherency enables design teams to improve SoC performance, it adds significantly to verification complexity. The use of verification IP (VIP) enables engineers to validate such designs, although the VIP's effectiveness depends on its advanced... » read more

Blog Review: Nov. 20
By Ed Sperling - 20 Nov, 2013 - Comments: 0

Can you really heat your home office with just four candles? It all depends on where you put those candles, as Mentor’s Robin Bornoff shows in part one of this series. And make sure you check out the video, particularly if you’ve had a tough day. Synopsys’ Karen Bartleson interviews ST’s Oleg Logvinov on camera about the IoT, which may be the biggest change since the Industrial Revol... » read more

The Week in Review: System-Level Design
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

Blog Review: Nov. 13
By Ed Sperling - 13 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory digs into optimal paths—in this case between the bakery, the library and another store. This is the classic traveling salesman equation, but with a large sales staff and lots of stops. Mentor’s Michael Ford points to the gap between supply-chain and shop-floor management solutions. This is yet another example of thinking outside the package—and maybe the enti... » read more

Executive Viewpoint: Atoptech’s Jue-Hsien Chern
By Brian Bailey - 13 Nov, 2013 - Comments: 0

What is the difference between skyscrapers and chips? Dr Chern has worked on both and he says it’s all about how you apply margins. Jue-Hsien Chern started his technology career earning a M.S. and B.S. in Engineering from National Taiwan University and majored in structural engineering — bridges, dams, tunnels and high-rise buildings, all of which had to withstand earthquakes. That is a ... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 11 Nov, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications
By Various Writers - 07 Nov, 2013 - Comments: 0

Synopsys is a leading EDA company with an extensive portfolio of licensable DesignWare intellectual property (IP). The portfolio includes interface IP, analog IP, embedded memories, and logic libraries. Although most chip designers know that DesignWare IP also includes licensable CPU cores and subsystems, many are surprised to learn that Synopsys is second only to ARM in the number of chips tha... » read more

FinFET Impacts For Reducing Physical IP Power Consumption
By Navraj Nandra - 07 Nov, 2013 - Comments: 0

FinFET devices were developed to address the need for improved gate control to suppress leakage current (IOFF); DIBL (drain-induced barrier lowering); and process‐induced variability below 32-nanometer. FinFET technology is now in volume production. To fully realize the advantages of FinFET devices, physical IP must follow the same trajectory that has benefited digital design. That include... » read more

Paving The Way To 16/14nm
By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

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