tag: Synopsys

VP Software Debugging: Myths And Facts
By Achim Nohl - 22 Sep, 2011 - Comments: 0

By Achim Nohl In my last post I introduced the debugging challenges during porting, or developing native code, for Android. This time I would like to outline how virtual prototypes can enable software debugging and perform in an even better way. Before I describe what “better” refers to exactly, I want to shed some light on some prominent myths around the value of VPs for debugging. W... » read more

Solid Verification Methodology Essential To Productivity
By Ann Mutschler - 22 Sep, 2011 - Comments: 0

Verifying SoCs from a functional perspective pushes the limits of already lean resources, driving verification teams to seek out new ways to improve productivity of verification tasks. Of course, with the verification task being a time-bound one, the challenge is daunting. It is well understood that consumer electronics is pushing the technology envelope in terms of the amount of technology ... » read more

20nm IP Portability Appears Virtually Impossible
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Each node on the deep submicron path has brought new challenges to engineering teams, and 20nm is no different. With EUV (extreme ultraviolet) lithography challenges still being worked out, double patterning (DP) instead will be embraced in the manufacturing process most likely until 10nm. Due to the unique nature of DP, IP portability between foundries will become a ... » read more

DFT: Essential For Power-Aware Test
By Ed Sperling - 18 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various low-power design technologies. Challenges for test engineers and test tool developers include understanding the various concerns associated with power-aware test, develo... » read more

A Different Kind Of Design
By Ed Sperling - 16 Sep, 2011 - Comments: 0

Intel’s announcements at the Intel Developer Forum this week that it will be creating physically smaller packages that can run on far less energy raises some interesting questions about the future of all design. We’ve become accustomed to one-chip implementations, whether that’s a monolithic processor or an SoC with lots of processors. In the future, though, there may be multiple chips, a... » read more

TSVs Ease Heat In 3D ICs
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler In the evolving discussion of 3D ICs and through silicon via (TSV) technology, a key issue engineering teams are facing today is how to reduce the thermal coefficients between substrates in a stacked die. Simply put, what is the best way to get the heat out of the 2.5 or 3D IC? The answer, of course, is anything but simple. “In a 3D system, the heat hierarchy ... » read more

Heat Wreaks Havoc
By Ed Sperling - 08 Sep, 2011 - Comments: 0

By Ann Steffora Mutschler As semiconductor manufacturing technology has scaled ever smaller, the density of power grid networks has caused on-chip temperatures to rise, negatively impacting performance, power, and reliability. CMOS technology, still the predominant material in SoCs, was originally conceived as a low-power technology when compared with the bipolar approach, which was a very... » read more

Will Wide I/O Reduce Cache?
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler In an ideal world, all new SoC technologies would make the lives of design engineers easier. While this may be true of some techniques, it is not the case with one advanced memory interface technology on the horizon, Wide I/O. There are claims that Wide I/O could reduce cache, but so far this is not widely understood. In fact, exactly how Wide I/O will be used, wha... » read more

Wide I/O’s Impact On Memory
By Ed Sperling - 25 Aug, 2011 - Comments: 0

By Ann Steffora Mutschler Driven by the need to reduce power but increase bandwidth in smart phones and other mobile devices, system architects are grappling with new technologies to take system performance to the next level. Wide I/O, as well as some DDR technologies, are vying for center stage in tomorrow’s leading-edge mobile designs. “The big technological advancement that allows a ... » read more

Getting The Balance Right
By Ann Mutschler - 11 Aug, 2011 - Comments: 0

Defining the power architecture for a low-power design means striking a balance between the high-level abstraction and measurements made typically at RTL and below, but today that is easier said than done. “The balance is that at the high level of abstraction, the design choices you make have a big effect over power, yet your ability to measure them is incomplete until you get much further... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy