tag: Synopsys

The Week In Review: Design
By Ed Sperling - 25 Apr, 2014 - Comments: 0

M&A Cadence announced its intention to acquire Jasper Design Automation, adding formal technology to its roster of verification tools. The purchase price was about $146 million, the $170 million Cadence offered minus the $24 million in cash and equivalents on Jasper’s books. Tools Synopsys rolled out new LPDDR4 IP that offers up to 3.2 Gbps with low power consumption. The company is ... » read more

What Are EDA’s Big Three Thinking?
By Ed Sperling - 24 Apr, 2014 - Comments: 4

Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult... » read more

Graphing Toward Standardization
By Brian Bailey - 24 Apr, 2014 - Comments: 0

Graph-based verification has become the hot topic of the day. It commanded a lot of attention at the recent DVCon, promises to fix many of the problems plaguing functional verification, can provide an automated way to perform system-level verification, enables portability of tests between simulation, emulation and prototyping, reduces the wastage created by constrained random test pattern gener... » read more

How To Improve Debug Productivity
By Ann Mutschler - 24 Apr, 2014 - Comments: 0

In the realm of SoC verification world, it often takes a very short amount of time to write the testbench and the code, and the rest of the time — up to 90% — is spent debugging. After all, verification is essentially finding the bugs in a design. Debugging essentially has evolved over the years on the same path and complexity curve as design. Now debugging needs to evolve to keep pace, ... » read more

Efficiency Metrics Get Fuzzy
By Ed Sperling - 24 Apr, 2014 - Comments: 0

Not too long ago chipmakers used to measure transistors per hour and software developers would measure lines of code written per day or per week. Those metrics have fallen by the wayside—and chipmakers are still lamenting that loss. The problem is that nothing has come along to replace the old metrics, and complexity has left many chipmakers scratching their heads about how to build effici... » read more

Extending UVM To Analog
By Ann Mutschler - 24 Apr, 2014 - Comments: 2

As SoC complexity has grown, so too has the need to model the analog/mixed-signal content in a similar way as the digital content to make simulation easier. One way to do this is within the context of the Universal Verification Methodology (UVM). In fact, this can and is being done today with UVM as it stands, according to a number of industry sources. However, there is also growing interest... » read more

What Should I Build?
By Tom De Schutter - 24 Apr, 2014 - Comments: 0

The question in the title has been one of the most asked questions by my son lately. Or as my wife says, his brain is 90% focused on Minecraft and 10% on everything else. For those not familiar with Minecraft, it is a lego-like computer game or as the Minecraft website reads: “Minecraft is a game about breaking and placing blocks.” It has literally captured the imagination of my son and ... » read more

Rethinking SoC Verification
By Various Writers - 23 Apr, 2014 - Comments: 1

The introduction of the iPhone in 2007 represented a fundamental shift in electronic system design: moving advanced processing power off of the desktop and into the hands of users everywhere, always. This shift has led to a revolution in mobile—the expansion into the Internet-of-Things, with wearables, connected automobiles and homes. This revolution is causing profound technology challeng... » read more

Blog Review: April 23
By Ed Sperling - 23 Apr, 2014 - Comments: 0

Mentor’s John Day looks backward through a smart rearview mirror from Nissan. No glare, even at night or at sunset, and a wider field of vision. You have to wonder why this technology took so long. Synopsys’ Karen Bartleson wonders when the IoT will actually arrive, given the delay in durable goods, a concern over security and the effects of government regulation. Answer: When we stop ta... » read more

The Week In Review: Design
By Ed Sperling - 18 Apr, 2014 - Comments: 0

Certifications TSMC certified Mentor Graphics’ DFM, place and route and custom IC tools, as well as its SPICE simulator, for the 16nm finFET process.  The foundry also certified Cadence’s digital and custom/analog tools for that process, including physical verification, QRC extraction, timing sign off and its power integrity solution. And it certified Synopsys’ digital and custom soluti... » read more

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