tag: Synopsys

What If EUV Fails?
By Mark LaPedus - 17 Apr, 2014 - Comments: 2

It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

Blog Review: April 16
By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

A Guide To Advanced Process Design Kits
By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

Architecting For Efficiency
By Ann Mutschler - 10 Apr, 2014 - Comments: 0

By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions. Efficiency comes in multiple ways. “One dimension would be power consumption,” said Oz Le... » read more

Power Moves Up To First Place
By Ed Sperling - 10 Apr, 2014 - Comments: 2

Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

Executive Insight: Simon Davidmann
By Brian Bailey - 10 Apr, 2014 - Comments: 0

Every industry has some colorful characters and within the EDA industry, Simon Davidmann is certainly one that comes to mind. For the past 30-something years, Davidmann has provided guidance to the industry, stood up for what he believes in, been an inspiration to many entrepreneurs, and had some fun along the way. Simon is a serial entrepreneur, angel investor and he has been a key person invo... » read more

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

Rethinking Low Power Verification
By David Hsu - 10 Apr, 2014 - Comments: 0

The discussion of low power verification has been centered around design complexity growth multiplied (or exponentiated) by growth in adoption of low power design techniques. The main objectives seem clear – ensure that: The specification for the low power intent is valid The low power implementation matches the specification, and that its architecture, structure and behavior is valid ... » read more

Advanced Dynamic Power Reduction Techniques
By Various Writers - 09 Apr, 2014 - Comments: 0

Rapid changes in SoC power issues have forced a rethinking of methodologies throughout the design flow to account for power-related effects. At 65 nanometer process nodes and below, leakage power and dynamic power consumption make it increasingly difficult to meet power budgets. Achieving timing and signal integrity closure is now tightly coupled with power optimization and power net distributi... » read more

Blog Review: April 9
By Ed Sperling - 09 Apr, 2014 - Comments: 0

Mentor’s Colin Walls discovered an interesting video of the software programming learning process—a teacher responding literally to commands from his students on how to make a jam sandwich. It’s harder than it looks. Cadence’s Brian Fuller captures a speech by his colleague, Sanjiv Taneja, about the need for a comprehensive verification approach and smart IP reuse. The overriding th... » read more

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