A Guide To Advanced Process Design Kits

A primer on the use and importance of PDKs in wafer fabrication.


The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) and other general or specialized process building blocks. This article will explain what a PDK is, how it is implemented, and use the design rule constraints tool within the PKD, as the example.

What Are PDKs?
Process design kits consist of a set of files that typically contain descriptions of the basic building blocks of the process. They are expressed, algorithmically, as Pcells. These descriptions are stored in standardized Pcells libraries, design rules and rule constraints, schematics, SPICE model of transistors and other components, and layout information. They are used to describe, precisely, manufacturing process details for designers and design tools. The contents of the file will vary depending upon the target component, but they are all based upon the GDSII stream format.

PDK incarnations can involve any number of automated routine and rules. For example, arranging and routing programmable cells and analyzing the cell arrangement and interconnect wiring for optimum manufacturing. Other approaches can perform wire analysis and placement to prevent shorting. In other rules, the reliability of contacts and vias will be optimized by adding or subtracting additional metallization to the areas surrounding the contacts and vias. In still other cases, redundant contacts and vias may be adding to optimize efficiently manufacturability. Or, design and layout improvements can be made to cells in an iterative fashion.

PDKs will vary depending upon the specific device itself and their respective models. PDKs are generally specific to each foundry and the specific project or technology. Advanced PDKs contain specialized or proprietary data and/or functions, as well. The large foundries can offer a front-to-back integrated custom design environment that supports all major electronic data (EDA) vendors’ design flows. The major vendors include Synopsys, Lorenz Solutions, Helic, Cadence, Mentor Graphics, Ansys-Apache, and others.

The reason that PDKs have become the de-facto design approach to today’s semiconductor design is due to the complexities and ever-shrinking, ever-denser designs of new component technology. In a nutshell, PDKs automatically do the modifying and verification of the design modifications of complex semiconductor designs. This has antiquated the traditional top-down approach in favor of a new “parallel bottoms-up” verification approach that PDKs implement.

High Level Overview – How They Work
The PDKs make, and store, a “representation” for each of the components. This representation is defined by standard rules such as the minimum channel length of the transistor, well-to-well spacing, minimum metal width and metal to metal spacing, electrostatic discharge (ESD) and I/O rules. The automatic constraints of the area and perimeter of the diffusion of applicable components, setting limits for min and max feature sizes and verifying hotspots can be part of the representation, as well.

The PDKs purpose is to automatically adjust, depending on the data of the parameters stored in the file, the design layout for producibility and manufacturability. For example, if a particular PKD design rule is applied to the contact area, if it is made larger by the designer, the particular design rule constraint (DRC) for this component may instruct additional contact openings to be created, some others removed, or existing or new resized, etc. Exactly how this is implemented is defined in the specific PDK. The PDK will also automatically set these constraints for the designer and will allow only certain parameters to be varied during the evaluation of designs. Again it depends upon the specific parameters of the definitions within the particular PDK. The advantage of this approach is that the final designs are guaranteed to be perfectly compatible with the manufacturing process. This streamlines the design process, maximizing productivity and minimizing costs and providing the customer with a maximum value proposition.

In The Trenches – Comprehending Process Complexity
Today’s processes have become unfathomably complex. It is impossible for the designer to optimize, manually, semiconductor and other component design with any degree of efficiency. Today’s complex processes include functions such as double patterning, dual stress liners and double-exposure vias. This, in turn, has necessitated the need for an increasing number of design rules, which in turn, demands tighter uniformity control. All of this means that the post-layout verification is much more sophisticated, and cannot be verified without edge-of-the-envelope EDA software. Therefore, the only practical approach is to work with PDKs.

A typical PDK will have a number of modules that will be correlated with the PDK. These include

  • Device models, which address shallow-trench isolation (STI), well proximity effect (WPE) and performance.
  • Design for manufacturing (DFM) awareness, which implements design rule constraint (DRC), CFM Rules and Fill Generation
  • Flow and Methodologies, which analyze and implement functional designs, verification and optimization and signoff for manufacturing.
  • Lithography/OPC, which performs the hotspot verification, litho redesign and printability.

All of these modules have to be synchronized with the PDK, adding another level of complexity to the design flow. Today’s approach to PDKs is a different, more “holistic” integration where each peripheral process is optimized and synchronized to the specific technology or product design flow. And, has semiconductor parameters scale downward and densities increase, additional functions will be required to be integrated into the PDK.

An Example of an advanced PDK Element – Design Rule Constraints
Design rule constraints are one of the key processes in a PDK. Design rule constraints are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit designs to standardized physical and electrical manufacturability criterion.

Today’s component miniaturization and density technologies require continual reassessment of best-of-breed applications to keep design geometries aligned with realistic manufacturing capabilities. Even though two-dimensional DRC layout patterns may prove to be mathematically and layout rules compliant, when they are applied at the extremes of the manufacturing process tolerances, lithographic printability issues still arise.

Advanced DRCs are designed to identify 2D pattern anomalies during all stages of the design flow, not just in the early stages of the design process. Advanced DRCs function in the same fashion as traditional design constrained applications. However, it adds the function of associating a 2D pattern to each constraint, which acts as a filter to localize where the constraint is applied. This translates into, when the DRC tool is running, a DRC rule deck. It will enforce tighter constraints only where the anomalies occur. For this discussion, tip-to-side patterns are the subject.

An example of this is when a typical U-shaped trace is laid down on a substrate and is subject to manufacturability constraints. DRCs can have a rule such as a tighter min_space +20-nm line-end space constraint where the U-shaped pattern is found. The reason for this rule can vary, but it isn’t important for this discussion other than the assumption that a tighter than standard rule is required. For this discussion, the technology must be constrained to manufacturability capabilities, so the PDK’s DRCs contain rules to that effect. The advantage of integrating DRCs into this PDK is because it can operate strictly on design geometries without any intrinsic understanding of the underlying manufacturing technology process. Thusly, the design can be held to the manufacturability criterion, regardless of the design itself.

Referring to the aforementioned U-shaped trace, assume the parameter of interest is the side-to-tip pattern. Each DRC rule includes a specific tip-to-side pattern, and a preferred rule. The preferred rule has a more stringent constraint applied in this pattern situation, because of a different design condition. In this case, the standard spacing may work well at a lower frequency, but the same design is being considered for use with higher data rates or frequencies. Design analysis indicates that the standard parameter of 60-nm may cause crosstalk or intermod to affect adjacent circuits at the new frequency, from some of the traces.

The engineer would then go back and rework the design accordign to the preferred rule analyitcs and reposition or rework traces that could potentially emanate electromagnetic (EM) or radio (RF) interference at the new frequency.

A Bit More Detail
Once the design has been reworked, DRCs are used to determine printability and manufacturability also. Say, for example, the preferred DRC rule in the PDK applies a more stringent constraint of ≥ 80 nm. This is done by first using the DRC to identify pattern configurations and develop situation classes by extracting patterns from representative designs. Once extracted, histograms of the situation classes are developed and these classes evaluated based upon permutations and occurrences.

The next step is to determine which of these situation classes have lower than average printability. These are the classes that, based upon the required constraint, ensure printability, become candidates for the DRC rule presented above. Next, a metric called design-induced edge printing variability (DIEPV) is used to determine the printability of each class. DEIPV essentially represents printing error over the process window for a given situation — the greater the magnitude of DIEPV, the more printing error is likely. To determine which situation classes are candidates for DRC rules, a simple threshold algorithm can be implemented, comparing the DIEPV statistics of each situation class to the values of the overall layout. One the algorithm has been applied the data can be displayed graphically for analysis.

Foundry PDKs and DRCs are compatible with both traditional and cutting-edge generation of EDA (Electronic Design Automation) tools. For the topic of this discussion, Calibre will be referenced. The equation-based DRC capability of Calibre provides specific suggestions on how to fix the violation. Where the physical verification platform is integrated into the physical design environment, most of the repairs can be done automatically by the physical design tool itself, such as the router.

DRCs use statistics derived from measurements of the situation classes as an alternative to simple CD (critical dimension) or EPE (edge placement error) thresholds used in classic printability verification. By identifying which situation classes have bad printability statistics, DRC rules can be algorithmically determined. Tools that provide fast pattern matching capabilities make implementation of DRC straightforward. For the user, it is mainly a matter of updating the standard DRC rule deck with the expanded DRC pattern-based rule deck provided by a particular foundry.

The above discussion has taken one element of the PDK and presented a scenario of how DRC+ is used to, algorithmically, characterize design variation through pattern classification. In new technologies such a 20-nm, traditional design rules are often limited to optimize the design flow and do not address new devices and parameters. This is why additional tools functions are developed which go beyond the traditional EDA tools.

DRC and the Graphical Design Rule Manual
Once the DRC has run an implemented the design constraints, if desired, the design errors can be presented. The reason for this is that often the complexities detailing the errors can be confusing, especially if it something new to the designer or an unfamiliar parameter. To that end, foundries have developed graphical design rule manuals (GDRMs).

Such manuals provide a graphical picture of each design rule, and is linked to, in this case, Calibre RVE files. When the DRC decks are run, if an error is discovered in the RVE file and further investigation is desired, selecting that error in the GDRM will take the designer to that specific error explanation and location. This helps to optimize design flow efficiency by reducing debug time and maximizes the value proposition. The result is that the GDRM provides the designer with a global roadmap that aids them in optimizing time and design efficiency.

DRC Flexibility and Customer Integration
Finally, process design kits are developed with designer focus in mind. To optimize the value of DRC tools, they must be capable of integrating with the customer’s IP. Customer-developed IP is a very valuable asset, and in many cases, unique to their designs. GlobalFoundries PDKs are very robust and can run DRCs on the clients IP, using the release candidate deck. Of course, close collaboration is required to define the IP blocks to be integrated with the PDK.

This article has been an mid-level discussed about PDKs, some of their variants, what they are and how they function.It has delved into details about process complexity and how it is addressed by tools within the PDK. It has gone on to further present an example of a tool within the PDK, specifically DRC tools and how they are implemented. It is hoped the reader will take away a basic comprehension of what they are and where they fit in the design process.


Brian Butcher says:

type-o’s man, very distracting… however I enjoyed reading it, thank you

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