tag: Synopsys

The Great Divide
By Ed Sperling - 27 May, 2010 - Comments: 0

By Ed Sperling One size no longer fits all, and that’s causing consternation across the supply chain from established EDA vendors to point tool developers all the way up to the largest chipmakers. While the overall number of design starts for SoCs really hasn’t changed much, despite a drop in the number of companies working at the most advanced process nodes, what has changed significan... » read more

TLM 2.0: Necessary for Co-Simulation
By Ann Mutschler - 27 May, 2010 - Comments: 0

By Ann Steffora Mutschler Transaction-level modeling – an abstracted representation of design IP above the RT level -- continues to grow in importance for architectural exploration, performance analysis, building virtual platforms for software development, and functional verification. The TLM-2.0 standard is the current industry standard for creating interoperable transaction-level models an... » read more

Unified Design Flows Require New Skill Sets
By Ed Sperling - 27 May, 2010 - Comments: 0

By Pallab Chatterjee With the release of the InRoute product from Mentor, three of the major EDA vendors now offer unified data model design flows that feature logic synthesis, physical synthesis, place and route, timing closure with high accuracy RC tools, and physical verification based on full process tools. These new tools were created to address the need for simultaneous Multi-Corner M... » read more

Same Industry, Different Shape
By Ed Sperling - 14 May, 2010 - Comments: 0

As the design industry plunges into DAC this year, it’s beginning to look like a completely different industry. It’s not the players themselves. There are still the Big Three EDA vendors, IP vendors and lots of startups. And it’s all still geared toward making chips. But the center of gravity has shifted from what was almost exclusively place and route and synthesis out to the edges of... » read more

A Shock To The System
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Electrostatic discharge used to be something confined to the I/O level, and often not even as part of the core design. But at 45nm and beyond, ESD is capable of wreaking havoc across a chip, blowing out transistors, wires and the insulation between them. What was once considered a sideshow in SoC development is becoming a central and critical issue at advanced nodes. The good... » read more

Making IP Tradeoffs For Power
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Power may be expensive, but just turning off sections of a chip, lowering the voltage or using low-power manufacturing processes have their own costs. Whether using power, or managing it, there is a price. As Brani Buric, executive vice president at Virage Logic says, “Power is not free.” But fortunately, other things in a design can be traded off in order to a... » read more

Experts At The Table: Verification Nightmares
By Ed Sperling - 13 May, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: How important is a high-leve... » read more

Experts At The Table: Verification Nightmares
By Ed Sperling - 23 Apr, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Shabtay Matalon, ESL marketing manager in Mentor Graphics’ Design Creation Division; Bill Neifert, CTO at Carbon Design Systems; Terrill Moore, CEO of MCCI Corp., and Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys. What follows are excerpts of that conversation. LPE: Where does power fit in? N... » read more

IP’s Ecosystem Race
By Ann Mutschler - 22 Apr, 2010 - Comments: 0

By Ann Steffora Mutschler As the semiconductor industry moves from older manufacturing nodes to newer ones what users want from IP providers is changing. So is the way IP providers are answering those needs. Mirroring the broader semiconductor industry’s recognition that it’s simply too expensive, too difficult and too time consuming to do everything alone—the very basis of the IP sec... » read more

Timing Bomb
By Ed Sperling - 22 Apr, 2010 - Comments: 0

By Ed Sperling Timing closure, a basic operation in chip design and development, is becoming anything but basic at advanced process nodes. Systematic variability that was at least predictable at 90nm has become random at 45nm. Tools that worked fine with two corner cases now have to deal with hundreds. And as more functions make their way onto a single die, often with multiple modes of oper... » read more

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